• Educational Technology International
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• 제18권2호
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• pp.131-157
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• 2017

The purposes of the study were to investigate the participation of artists in paper circuit computing learning and to conduct an in-depth study on the formation and development of practical knowledge. To do this, we selected as research participants six artists who participated in the learning program of an art museum, and used various methods such as pre-open questionnaires, participation observation, and individual interviews to collect data. The collected data were analyzed based on community of practice theory. Results showed that the artists participated in the learning based on a desire to use new technology or find a new work production method for interacting with their audiences. In addition, the artists actively formed practical knowledge in the curriculum and tried to apply paper circuit computing to their works. To continuously develop the research, participants formed a study group or set up a practical goal through planned exhibitions. The results of this study can provide implications for practical approaches to, and utilization of, paper circuit computing.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.49-54
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• 2010

This paper describes a fast circuit simulation technique using the latency insertion method (LIM) with a parallel and distributed leapfrog algorithm. The numerical simulation results on the PC cluster system that uses the cloud computing system are shown. As a result, it is confirmed that our method is very useful and practical.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.49-56
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• 2005

본 논문에서는 사용자로부터 테스트하고자 하는 고장 모델을 입력받아 적절한 much 테스트 알고리즘을 만들고 BIST 회로를 생성해 주는 Memory BIST Circuit Creation System(MBCCS) 을 제안하고 있다. 기존의 툴들은 널리 사용되고 있는 알고리즘에 국한되어 메모리의 사양이 변할 경우 거기에 맞는 BIST 회로를 다시 생성해주는 번거로움이 있었다. 하지만 본 논문에서 제안한 툴에서는 다양해진 메모리 구조에 적합한 메모리 BIST 회로를 사용자 요구에 맞는 알고리즘을 적용해서 자동적으로 생성하게 하였고, 임의적으로 선택된 고장 모델에 대한 알고리즘을 제안된 규칙에 따라 최적화함으로 해서 효율성을 높였다. 또한 다양한 크기의 폭을 갖는 주소와 데이터를 지원하며 IEEE 1149.1 회로와의 인터페이스도 고려하였다.

• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• Journal of Information Processing Systems
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• 제5권4호
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.425-429
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• 2014

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

• 실천공학교육논문지
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• 제10권1호
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• pp.49-56
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• 2018

비전공 학부생을 대상으로 다양한 방식의 SW 교육이 대학별로 운영되고 있다. 그리고 대부분 컴퓨팅적 사고를 교육하는 데 초점을 맞추고 있다. 이러한 컴퓨팅 교육에 이어서 학생들마다 창의적인 컴퓨팅 산출물을 구현하고 평가하는 교육 방식이 필요하다. 본 논문에서는 창의적 컴퓨팅 산출물 기반 SW교육을 실현하는 한 가지 방안을 제안한다. 이를 위해 학생들이 디지털논리회로 장치를 창의적으로 구현하고, 이 장치의 기능을 구현하는 SW알고리즘을 디자인하는 교육방법을 제안한다. 제안한 교육 방법에서는 아두이노 보드를 사용한 간단한 LED 논리회로를 예로 들어 교육한다. 학생들은 2변수 논리회로 출력장치 두 쌍을 창의적으로 설계 및 구현하고, 구현한 장치의 패턴을 나타내는 알고리즘을 다양한 형태로 설계한다. 그리고 입력장치를 이용한 기능 확장 및 확장된 알고리즘을 설계한다. 제안한 교육방법을 적용하면, 비전공 학생들이 창의적 컴퓨팅 산출물 제작을 통해 알고리즘 설계의 개념과 필요성을 습득하는 성과를 얻을 수 있다.

• 한국정보통신학회논문지
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• 제25권8호
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• pp.1060-1066
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• 2021

최근, 양자컴퓨터를 활용하기 위한 연구개발이 다양한 분야에서 활발하게 이루어지고 있다. 양자컴퓨터는 양자 얽힘, 양자중첩과 같은 다양한 양자역학의 현상과 특성을 활용하여 연산을 수행하기 때문에 기존 컴퓨팅 환경에 비해 아주 복잡한 연산과정을 거치게 된다. 이러한 양자컴퓨터를 구동하기 위해서는 연산에 활용되는 양자게이트의 구성뿐만 아니라 큐비트의 종류, 배치, 연결성 등 물리적인 양자컴퓨터의 요소를 반영한 알고리즘이 구성되어야 한다. 따라서 양자컴퓨터 구성요소들의 상호간 영향을 포함한 구성 정보를 직관적으로 파악할 수 있는 회로 시각화가 필요하다. 본 논문에서는 양자컴퓨터를 구성하는 양자칩 정보와 양자컴퓨팅 회로 데이터를 3D로 시각화하여 직관적으로 데이터를 관측하고 활용할 수 있도록 시각화 하여 직관적인 정보를 분석할 수 있는 방법을 제안한다.

• 대한전자공학회논문지
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• 제25권5호
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.