• Educational Technology International
• /
• v.18 no.2
• /
• pp.131-157
• /
• 2017

The purposes of the study were to investigate the participation of artists in paper circuit computing learning and to conduct an in-depth study on the formation and development of practical knowledge. To do this, we selected as research participants six artists who participated in the learning program of an art museum, and used various methods such as pre-open questionnaires, participation observation, and individual interviews to collect data. The collected data were analyzed based on community of practice theory. Results showed that the artists participated in the learning based on a desire to use new technology or find a new work production method for interacting with their audiences. In addition, the artists actively formed practical knowledge in the curriculum and tried to apply paper circuit computing to their works. To continuously develop the research, participants formed a study group or set up a practical goal through planned exhibitions. The results of this study can provide implications for practical approaches to, and utilization of, paper circuit computing.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.49-54
• /
• 2010

This paper describes a fast circuit simulation technique using the latency insertion method (LIM) with a parallel and distributed leapfrog algorithm. The numerical simulation results on the PC cluster system that uses the cloud computing system are shown. As a result, it is confirmed that our method is very useful and practical.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.49-56
• /
• 2005

In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.

• Journal of IKEEE
• /
• v.18 no.2
• /
• pp.228-233
• /
• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• Journal of Information Processing Systems
• /
• v.5 no.4
• /
• pp.187-196
• /
• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.1005-1008
• /
• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.6
• /
• pp.425-429
• /
• 2014

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

• Journal of Practical Engineering Education
• /
• v.10 no.1
• /
• pp.49-56
• /
• 2018

Various types of SW education are being operated by universities for non-major undergraduates. And most of them focus on educating computational thinking. Following this computing education, there is a need for an educational method that implements and evaluates creative computing outcomes for each student. In this paper, we propose a method to realize SW education based on creative computing artifacts. To do this, we propose an educational method for students to implement digital logic circuit devices creatively and design SW algorithms that implement the functions of their devices. The proposed training method teaches a simple LED logic circuit using an Arduino board as an example. Students creatively design and implement two pairs of two input logic circuit devices, and design algorithms that represent patterns of implemented devices in various forms. And they design the functional extension and extended algorithm using the input device. By applying the proposed method, non-major students can gain the concept and necessity of algorithm design through creative computing artifacts.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.8
• /
• pp.1060-1066
• /
• 2021

Recently, researches for quantum computers have been carried out in various fields. Quantum computers performs calculations by utilizing various phenomena and characteristics of quantum mechanics such as quantum entanglement and quantum superposition, thus it is a very complex calculation process compared to classical computers used in the past. In order to simulate a quantum computer, many factors and parameters of a quantum computer need to be analyzed, for example, error verification, optimization, and reliability verification. Therefore, it is necessary to visualize circuits that can intuitively simulate the configuration of the quantum computer components. In this paper, we present a novel visualization method for designing complex quantum computer system, and attempt to create a 3D visualization toolkit to deploy large circuits, provide help a new way to design large-scale quantum computing systems that can be built into future computing systems.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.5
• /
• pp.528-535
• /
• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.