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Evaluations on the Characteristics of Pressure Drop f3r the Design of Intravascular Artificial Lung Assist Device (혈관 내 폐 보조장치 설계를 위한 압력손실 특성 평가)

  • 김기범;권대규;박재관;정경락;이삼철
    • Membrane Journal
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    • v.13 no.1
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    • pp.20-28
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    • 2003
  • In this study, we try to formularize simultaneous equations to make a prediction about pressure drop for designing intravascular artificial lung assist device. Designing parameters to predict the effect of pressure drop and designed modules under various conditions were studied through an experimental modeling before inserting the artificial lung assist device into as venous. We measured pressure drop in various number of hollow fiber membranes, when the inside diameter of shell is fixed in 3 cm, and tried to develope the prediction equations by curve fitting based on the correlation between the experimental pressure drop and the device frontal area or packing density. The results showed that pressure drop increased with 2nd order functional formula as the liquid flow rate, the frontal area, and the packing density increased. Also, we can estimate the pressure drop as a function of the frontal area or packing density. The pressure drop obtained from the experiment was similar to that from the equation, confirming the usefulness of the equation.

Multi-scale heat conduction models with improved equivalent thermal conductivity of TRISO fuel particles for FCM fuel

  • Mouhao Wang;Shanshan Bu;Bing Zhou;Zhenzhong Li;Deqi Chen
    • Nuclear Engineering and Technology
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    • v.55 no.3
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    • pp.1140-1151
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    • 2023
  • Fully Ceramic Microencapsulated (FCM) fuel is emerging advanced fuel material for the future nuclear reactors. The fuel pellet in the FCM fuel is composed of matrix and a large number of TRistructural-ISOtopic (TRISO) fuel particles which are randomly dispersed in the SiC matrix. The minimum layer thickness in a TRISO fuel particle is on the order of 10-5 m, and the length of the FCM pellet is on the order of 10-2 m. Hence, the heat transfer in the FCM pellet is a multi-scale phenomenon. In this study, three multi-scale heat conduction models including the Multi-region Layered (ML) model, Multi-region Non-layered (MN) model and Homogeneous model for FCM pellet were constructed. In the ML model, the random distributed TRISO fuel particles and coating layers are completely built. While the TRISO fuel particles with coating layers are homogenized in the MN model and the whole fuel pellet is taken as the homogenous material in the Homogeneous model. Taking the results by the ML model as the benchmark, the abilities of the MN model and Homogenous model to predict the maximum and average temperature were discussed. It was found that the MN model and the Homogenous model greatly underestimate the temperature of TRISO fuel particles. The reason is mainly that the conventional equivalent thermal conductivity (ETC) models do not take the internal heat source into account and are not suitable for the TRISO fuel particle. Then the improved ETCs considering internal heat source were derived. With the improved ETCs, the MN model is able to capture the peak temperature as well as the average temperature at a wide range of the linear powers (165 W/cm~ 415 W/cm) and the packing fractions (20%-50%). With the improved ETCs, the Homogenous model is better to predict the average temperature at different linear powers and packing fractions, and able to predict the peak temperature at high packing fractions (45%-50%).

Studies on the Utilization of Persimmons -(Part 5) Investigation of the Optimum Thickness of Film Bag for Poly Ethylene Film Storage of Astringent Variety- (감의 이용(利用)에 관(關)한 연구(硏究) -(제5보(第五報)) 삽시의 Polyethylene Film 저장(貯藏)에 따른 최적(最適) Film 두께의 조사(調査)-)

  • Sohn, T.H.;Choi, C.J.;Cho, R.K.;Seog, H.M.;Seong, C.H.;Seo, O.S.;Ha, Y.S.;Kang, J.H.
    • Korean Journal of Food Science and Technology
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    • v.10 no.1
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    • pp.73-77
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    • 1978
  • This experiment was made to select the optimum thickness of the polyethylene (P.E) film for Cheongdo Bansi and Sagoksi in the P.E film storage kept at $0^{\circ}C$. The experimental plots were divided into 4 plots by film thickness (0.04, 0.06, 0.08 and 0.10mm) and those were subdivided into 3 plots by fruits number (3, 10 and 50 persimmons) in each film bags. We investigated five experimental items; the change of loss of weight, firmness, titratable acidity, sugar contents and soluble tannin contents. 1. In the changes of loss of weight, the plot of packing in 0.04mm P.E. film bag with 50 persimmons were more retarded than other plots in Cheongdo Bansi, and packing in 0.08mm with 10 persimmons, 0.04 mm with 50 persimmons were more retarded than other plots in Sagoksi. 2. In the change of softening, the plot of packing in 0.04 mm with 50 persimmons were more retarded than other plots in Cheongdo Bansi and Sagkai. 3. In the changes of titratable acidity, the plot of packing in 0.04 mm with 50 persimmons were more slightly decreased than other plots in Cheongdo Bansu also in Sagoksi, packing in 0.06 mm with 10 persimmons were the same results. 4. In the changes of soluble tannin contents, the plots of packing in 0.06 mm with 10 persimmons, 0.04 mm with 50 perimmons were more ratarded in Chenongdo Bansi, also in Sagoksi, packing in 0.04 mm with 10 persimmons 50 persimmons were the same results. 5. In the changes of soluble tannin contents, the plots of packing in 0.04mm with 3 and 10 persimmons were more slowly decreased than other plots in Cheongdo Bansi and Sagoksi, on. the other hand, pcaking in 0.04mm with 50 persimmins in Cheongdo Bansi and Sagoksi, had not astringent taste at 120 days in storage. Judging through the upper results, the most desirable storage conditions for Cheongdo Bansi and Sagoksi were to pack in P.E film bag of 0.04mm with 50 persimmons.

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A CLB based CPLD Low-power Technology Mapping Algorithm (CLB 구조의 CPLD 저전력 기술 매핑 알고리즘)

  • 김재진;윤충모;인치호;김희석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1165-1168
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    • 2003
  • In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

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TOPOLOGICAL MAGNITUDE OF A SPECIAL SUBSET IN A SELF-SIMILAR CANTOR SET

  • Baek, In-Soo
    • The Pure and Applied Mathematics
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    • v.14 no.1 s.35
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    • pp.1-5
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    • 2007
  • We study the topological magnitude of a special subset from the distribution subsets in a self-similar Cantor set. The special subset whose every element has no accumulation point of a frequency sequence as some number related to the similarity dimension of the self-similar Cantor set is of the first category in the self-similar Cantor set.

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An Efficient CPLD Technology Mapping considering Area under Time Constraint (시간 제약 조건하에서 면적을 고려한 효율적인 CPLD 기술 매핑)

  • Kim, Jae-Jin;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.79-85
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    • 2001
  • In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

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Optimization of Multiple Quality Characteristics for Polyether Ether Ketone Injection Molding Process

  • Kuo Chung-Feng Jeffrey;Su Te-Li
    • Fibers and Polymers
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    • v.7 no.4
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    • pp.404-413
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    • 2006
  • This study examines multiple quality optimization of the injection molding for Polyether Ether Ketone (PEEK). It also looks into the dimensional deviation and strength of screws that are reduced and improved for the molding quality, respectively. This study applies the Taguchi method to cut down on the number of experiments and combines grey relational analysis to determine the optimal processing parameters for multiple quality characteristics. The quality characteristics of this experiment are the screws' outer diameter, tensile strength and twisting strength. First, one should determine the processing parameters that may affect the injection molding with the $L_{18}(2^1{\times}3^7)$ orthogonal, including mold temperature, pre-plasticity amount, injection pressure, injection speed, screw speed, packing pressure, packing time and cooling time. Then, the grey relational analysis, whose response table and response graph indicate the optimum processing parameters for multiple quality characteristics, is applied to resolve this drawback. The Taguchi method only takes a single quality characteristic into consideration. Finally, a processing parameter prediction system is established by using the back-propagation neural network. The percentage errors all fall within 2%, between the predicted values and the target values. This reveals that the prediction system established in this study produces excellent results.

Development of Pilot-Scale Scrubber for Simultaneous Removal of $SO_2/NO$

  • Jung, Seung-Ho;Jeong, Gwi-Taek;Lee, Gwang-Yeon;Park, Don-Hee;Cha, Jin-Myeong
    • 한국생물공학회:학술대회논문집
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    • 2005.10a
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    • pp.468-474
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    • 2005
  • SOx and NOx are known major precursors of acid rain and thus the abatement of their emissions is a major target in air pollution control. To obtain basic data on the removal process of simultaneous $SO_2/NO$, the optimal reaction condition and the composition of reaction solution for simultaneous removal of $SO_2/NO$, ware investigated using a bubble column reactor. Pilot scrubber was consisted of scrubber, filter and control box. Dust removal rate was 83, 92, and 97% with catalyst flux of 0.5, 0.8, 1.5 L/min, respectively Average dust removal efficiency with a kind of nozzle was about 94 and 90% in STS FF6.5 (5/8in.) and 14 of P.P W(1.0in.), respectively Dust and $SO_2$ were removed more than 98-96% regardless of reactor number. In the case of NO gas, removal yield of 83.3% was achieved after 48 hours in 1 stage, also removal yield of 95.7% was reached in 2 stages. In tile case of application of STS (5/8 in.) and P.P (1.0 in.) as used fill packing, removal efficiency was reached higher than 98% without related to of kind of fill packing.

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Development of CPLD Technology Mapping Algorithm for Sequential Circuit Improved Run-Time Under Time Constraint (시간제약 조건하에서 순차 회로를 위한 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발)

  • Yun, Chung-Mo;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.80-89
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    • 2000
  • In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

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Development of CPLD technology mapping algorithm for Sequential Circuit under Time Constraint (시간제약 조건하에서 순차 회로를 위한 CPLD 기술 매핑 알고리즘 개발)

  • Youn, Chung-Mo;Kim, Hi-Seok
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.1
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    • pp.224-234
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    • 2000
  • In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

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