• 대한기계학회논문집A
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• 제38권10호
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• pp.1049-1056
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• 2014

전자 부품을 이루고 있는 재료들은 여러 다른 열팽창계수를 가지고 있다. 새롭게 개발된 재료나 적용하려는 온도범위가 다른 경우에는 실제 제품을 구성하고 있는 그 재료 자체의 열팽창계수를 측정할 필요가 있으며 이에 대한 신뢰성 있는 측정방법이 필요하다. 재료의 온도가 변화하면, 그에 부착된 스트레인 게이지 저항체의 출력은 기계적인 하중뿐 아니라 온도변화에 의해서도 복합적으로 발생한다. 본 논문에서는 이러한 스트레인 게이지의 특성을 이용하여 온도가 증가함에 따라 변하는 변형률을 측정하고 이로부터 재료의 열팽창계수를 구하는 방법을 실험적으로 제시하였다. 실험의 신뢰성을 검증하기 위해서 일반적으로 열팽창계수가 잘 알려진 탄소강, 알루미늄 및 구리시편을 사용해서 열팽창계수를 측정하고 그 결과를 비교하여 열팽창계수 측정방법의 신뢰성을 평가하였다. 또한 이 방법을 전자 패키지를 구성하고 있는 새로운 전자재료에 적용하여 무섬유 패키지 기판의 온도에 따른 열팽창계수를 측정하였다.

• 대한기계학회논문집A
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• 제28권4호
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.633-636
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• 2006

GE has developed a plastic substrate technology comprised of a superior high-heat polycarbonate substrate film and a unique transparent coating package that provides the ultrahigh barrier to moisture and oxygen, and chemical resistance to solvents used in device fabrication. This contribution will update recent progresses made at GEFlexible Ultra-high Gas Barrier Substrate for Organic Electronics on ultra-high barrier coated plastic substrate, both in batch mode and in roll-to-roll mode

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• 조명전기설비학회논문지
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• 제29권4호
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• pp.1-10
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• 2015

The light emitting diodes(LED) package of new structure is proposed to promote the reliability and lifespan by maximize heat dissipation occurred on the chip. We designed and fabricated the LED packages mixing the advantages of chip on board(COB) based on conventional metal printed circuit board(PCB) and the merits of Si sub-mount using base as a substrate. The proposed LED package samples were selected for the superior efficiency of the material through the sealant properties, chip characteristics, and phosphor properties evaluations. Reliability test was conducted the thermal shock test and flux rate according to the usage time at room temperature, high-temperature operation, high-temperature operation, high-temperature storage, low-temperature storage, high-temperature and high-humidity storage. Reliability test result, the average flux rate was maintained at 97.04% for each items. Thus, the Si sub-mount based LED package is expected to be applicable to high power down-light type LED light sources.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• 조명전기설비학회논문지
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• 제30권3호
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• pp.30-38
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• 2016

In this research, a 6W white LED package with a Glass Remote Phosphor was developed to improve the life of an LED package. The Glass Remote Phosphor was fabricated by the Phosphor in Glass (PiG) method, wherein phosphor YAG:Ce was mixed with glass frit and then heat treated. A paste with 75wt.% of a phosphor substance and 25wt.% glass frit was coated on a glass substrate two times using the screen-printing technique and heat-treated at $800^{\circ}C$ ; this structure gave a luminous efficacy of 136.1lm/W, color rendering index of 74Ra, and color temperature of 5,342K, thus satisfying the requirements as a light source for lighting. Moreover, an IES LM-80 accelerated life test was conducted on the same LED package for 6,000h in order to estimate the L70 lifetime based on IES TM-21. The results showed guaranteed lifetimes of 213,000h at $55^{\circ}C$, 245,000h at $85^{\circ}C$, and 209,000h at $95^{\circ}C$.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.597-598
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• 2006

This paper describes a development of a new $1.4{\times}1.1$ and $2.0{\times}1.4mm$ RF SAW filters made by PCB substrate instead of HTCC package, and this technology can reduce the cost of materials down to 40%. We have investigated the multi-layered PCB substrate structures and raw materials to find out the optimal flip-bonding condition between the $LiTaO_3$ wafer and PCB substrates. Also the optimal materials and processing conditions of epoxy laminating film were found out through the experiments which can reduce the bending moment caused by the difference of the thermal expansion between the PCB substrate and laminating film. The new PCB SAW filter shows good electrical and reliability performances with respect to the present SAW filters.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.445-446
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• 2007

The use of plastic substrates enables new applications, such as flexible display devices, and other flexible electronic devices, using low cost, rollto-roll (R2R) fabrication technologies. One of the limitations of polymeric substrate in these applications is that oxygen and moisture rapidly diffuse through the material and subsequently degrade the electro-optical devices. GE Global Research (GEGR) has developed a plastic substrate technology comprised of a superior high-heat polycarbonate (LEXAN(R)) substrate film and a unique transparent coating package that provides the ultrahigh barrier (UHB) to moisture and oxygen, chemical resistance to solvents used in device fabrications, and a high performance transparent conductor. This article describes the coating solutions for polycarbonate (LEXAN(R)) films and its compatibility with OLED device fabrication processes.