• Journal of Welding and Joining
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• 제16권5호
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• pp.100-107
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• 1998

This paper describes fluxless soldering of reflow soldering process using solder foil instead of solder pastes. There is an increasing demand for the reliable solder connection in the recent high density microelectronic components technologies. And also, it is problem fracture of an Ozone layer due to freon as which is used to removal of remained flux on the substrate. This paper discussed joining phenomena, boudability and joining processes of microelectronics devices, such as between outer lead of VLSI package and copper pad on a substrate without flux. The shear strength of joints is 8 to 13 N using Sn/Pb (63/37 wt.%) solder foil with optimum joining conditions, meanwhile, in case of using Sn/In (52/48 wt.%) solder foil, it is possible to bond with low heating temperature of 550 K, and accomplish to high bonding strength of 25N in condition heating temperature of 650K. Finally, this paper experimentally shows fluxless soldering using solder foil, and accomplishes key technology of microsoldering processes.

• ETRI Journal
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• 제33권5호
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• pp.802-805
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• 2011

This letter presents a K-band polarization reconfigurable antenna integrated with a silicon radio frequency MEMS switch into the form of a compact package. The proposed antenna can change its state from linear polarization (LP) to circular polarization (CP) by actuating the MEMS switch, which controls the configuration of the coupling ring slot. Low-loss quartz is used for a radiating patch substrate and at the same time for a packaging lid by stacking it onto the MEMS substrate, which can increase the system integrity. The fabricated antenna shows broadband impedance matching and exhibits high axial ratios better than 15 dB in the LP and small axial ratios in the CP, with a minimum value of 0.002 dB at 20.8 GHz in the K-band.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1504-1505
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• 2007

In this paper, fully embedded high Dk BTO MIM capacitors have been developed into a multi-layered organic package substrate for low cost RF SOP (System on Package) applications. These embedded MIM capacitors were designed and simulated by using CST 3D EM simulators for finding out optimal geometries and verifying their applicability. The embedded MIM capacitor with a size of $550\;{\times}\;550\;um^2$ has a capacitance of 5.3pF and quality factor of 43 at 1.5 GHz, respectively. The measured performance characteristics were well matched with 3D EM simulated ones. Equivalent circuit parameters of the embedded capacitors were extracted for making a design library.

• Journal of Welding and Joining
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• 제17권2호
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• pp.61-65
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• 1999

Because of the need for packages which accommodate high pin count, high density and high speed device, PBGA(plastic ball grid array) package gets more spotlight. But the substrate material which is used for PBGA package is in nature susceptible to moisture penetration. The objective of the study is to find out the path of delamination in the stacked structure of substrate. To increase the adhesion between the cooper laminate and PSR(photo solder resist) which is the weakest part, experiments were performed by changing parameters of printing pre-treatment and post-treatment process. As a result of experiments, the factor effects on the adhesion between the cooper laminate and PSR is caused by all of the pre-treatment and post-treatment condition. A considerable change was observed depending on the amount of UV irradiation after thermal cure which is typical of printing post-treatment condition rather than pre-treatment condition.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2007년도 SMT/PCB 기술세미나
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기물성,응용부문
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• pp.30-32
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• 2005

This paper reports on an LTCC-based packaging method using Au/Sn eutectic bonding process for RF MEMS applications. The proposed packaging structure was realized by a micromachining technology. An LTCC substrate consists of metal filled vertical via feedthroughs for electrical interconnection and Au/Sn sealing rim for eutectic bonding. The LTCC capping substrate and the glass bottom substrate were aligned and bonded together by a flip-chip bonding technology. From now on, shear strength and He leak rate will be measured then the fabricated package will be compared with the LTCC package using BCB adhesive bonding method which has been researched in our previous work.

• 센서학회지
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• 제27권1호
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• pp.40-46
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• 2018

In this paper, we focus on optimization of a boron ($^{11}B$)-implanted n type Si epi substrate for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $125^{\circ}C$. The $^{11}B$-implantation on the N type-Si epi substrate formed isolation from the rest of the N-type Si by the depletion region of a PN junction. The TCR increased as the temperature of rapid thermal anneal (RTA) was increased at the temperature range from $900^{\circ}C$ to $1000^{\circ}C$ for the $p^+$ contact with implantation at dose of $1E16/cm^2$, but sheet resistance of this film was decreased. After the optimization of anneal process condition, the TCR of $1126.7{\pm}30.3$ (ppm/K) was obtained for the $p^-$ resistor-COB package chips contained $p^+$ contact with the implantation of $5E14/cm^2$. This shows the potential of the $^{11}B$-implanted n type Si epi substrate as a resistor for pressure sensor in thermal stable environment applications..

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2006년도 ISMP 2006
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• pp.67-73
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• 2006

A system in package (SiP) generally contains a variety of systems such as analog, digital, optical and micro-electro-mechanical systems, integrated in a system-level package connected through a substrate. However, there are many electrical and mechanical reliability issues including the reliability issue for embedded structures. A mismatch of thermal coefficients of expansion among packaging materials and devices can lead to warping or delamination in the package. In this study, the effect of material properties of underfill, such as Young's modulus and CTE, are investigated through FEM simulation. Experimental investigation on the warpage of the package is also carried out to verify the simulation results. The results show that the reliability of the system in package is closely related to the material properties of underfill. The results of this study provide a good guidance for the material selection when designing the system in package.

• 한국정밀공학회지
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• 제20권10호
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• 마이크로전자및패키징학회지
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• 제22권3호
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• pp.57-65
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• 2015

반도체 패키지는 여러 가지 다양한 재료로 구성되어 있으며, 제조시나 사용 환경에서 온도가 변하면 각 재료의 열팽창 계수의 차이로 인하여 굽힘변형이 발생하게 된다. 그림자 무아레 방법은 비접촉으로 전체 영역에 걸친 면외변위를 측정하는 광학적 방법이지만 측정 감도가 $50{\mu}m/fringe$ 이상이어서 반도체 패키지의 굽힘변형을 측정하기에는 적당하지 않은 면이 있었다. 본 논문에서는 그림자 무아레 시스템에 위상이동 기법을 적용하여 $12.5{\mu}m/fringe$의 향상된 감도를 갖는 측정장치를 구성하였다. 그림자 무아레 측정에서 나타나는 탈봇 현상을 고려하여 1/2 탈봇 영역에서 변형을 측정할 수 있도록 실험을 수행하였다. 위상이동에 의해 기록되는 4장의 그림자 무늬를 영상처리하여 감도가 4배 향상된 그림자 무늬를 얻어내었다. 본 논문에서 개발한 측정방법을 기존의 섬유강화 패키지 기판과 무섬유 패키지 기판에 적용하여 상온과 약 $100^{\circ}C$의 환경에서 발생하는 굽힘변형을 측정하였다.