• Journal of Electrical Engineering and Technology
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• v.2 no.2
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• pp.267-273
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• 2007

A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of $<\;3({\mu}m)$. For narrow-channel devices the variation of the threshold voltage was sharp for $<4({\mu}m)$ due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of $<\;4({\mu}m)$ and channel area of $<\;4{\times}4({\mu}m^2)$ respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.

• Computers and Concrete
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• v.29 no.4
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• pp.247-253
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• 2022

In this study, the problem of discontinuous contact in two functionally graded (FG) layers resting on a rigid plane and loaded by two rigid blocks is solved by the finite element method (FEM). Separate analyzes are made for the cases where the top surfaces of the problem layers are metal, the bottom surfaces are ceramic and the top surfaces are ceramic and the bottom surfaces are metal. For the problem, it is accepted that all surfaces are frictionless. A two-dimensional FEM analysis of the problem is made by using a special macro added to the ANSYS package program The solution of this study, which has no analytical solution in the literature, is given with FEM. Analyzes are made by loading different Q and P loads on the blocks. The normal stress (σy) distributions at the interfaces of FG layers and between the substrate and the rigid plane interface are obtained. In addition, the starting and ending points of the separations between these surfaces are determined. The normal stresses (σx, σy) and shear stresses (τxy) at the point of separation are obtained along the depth. The results obtained are shown in graphics and tables. With this method, effective results are obtained in a very short time. In addition, analytically complex and long problems can be solved with this method.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.39-43
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• 2009

In this paper, the flow characteristics of underfill material driven by capillary action between flip-chip and substrate were investigated. Also, the effects of viscosity level and dispensing point of underfill on flow characteristics were investigated. Flip chip package size was $5mm{\times}5mm{\times}0.65^tmm$, the diameter of solder bump was 100 ${\mu}m$, and the pitch was 150 ${\mu}m$. It was full grid area-array type with 1024 I/Os. The glass substrate was used and the gap between the chip and substrate was 50 ${\mu}m$. For the experimental study, three different underfills with different viscous properties($2000{\sim}3700$ cps), and two different types of dispensing methods(center dot and edge dot) were used. The flow characteristics and filling time of underfill were investigated by using CCD camera. The results show that the edge flow was faster than center flow due to the edge effect, which was caused by the resistance of solder bumps. In case of edge dot dispensing type, the filling time was faster due to the large edge effect, compared to center dot dispensing type. Also, it was found that the underfill flow was faster and the filling time decreased as the viscosity level of underfill was decreased.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.4
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• pp.290-298
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• 2018

Herein, an S-band internally-matched power amplifier that shows a power capability of 300 W in a Long Term Evolution(LTE) band 7 is designed and fabricated using a CGHV40320D GaN HEMT from Wolfspeed. Based on the nonlinear model, the optimum source and load impedance are extracted from the source-pull and load-pull simulations at the fundamental and harmonic frequencies, and the harmonic impedance tuning circuits are implemented inside a ceramic package. The internally matched power amplifier, which is fabricated using a thin-film substrate with a high relative permittivity of 40 and an RF35TC PCB substrate, is measured at the pulsed condition with a pulse period of 1 ms and a duty cycle of 10%. The measured results show a maximum output power of 257~323 W, a drain efficiency of 64~71%, and a power gain of 11.5~14.0 dB at 2.62~2.69 GHz. The LTE-based measurement shows a drain efficiency of 42~49% and an ACLR of less than -30 dBc(excluding 2.62 GHz) at an average power of 79 W.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.99-99
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• 2009

Two different micro-flows during the evaporation of ink droplets were achieved by engineering both surface tension gradient and compositional gradient across the ink droplet: (1) Coffee-ring generating flow resulting from the outward flow inside the ink droplet & (2) Marangoni flow leading to the circulation flow inside the ink droplet. The surface tension gradient and the compositional gradient in the ink droplets were tailored by mixing two different solvents with difference surface tension and boiling point. In order to create the coffee-ring generating flow (outward flow), a single-solvent system using N,N-dimethylformamide with nano-sized spherical alumina particles was formulated, Marangoni flow (circulation flow) was created in the ink droplets by combining N,N-dimethylformamide and fotmamide with the spherical alumina powders as a co-solvent ink system. We have investigated the effect of these two different flows on the formation of ceramic films by inkjet printing method, The packing density of the ceramic films printed with two different ink systems (single- and co-solvent systems) and their surface roughness were characterized. The dielectric properties of these inkjet-printed ceramic films such as dielectric constant and dissipation factor were also studied in order to evaluate the feasibility of their application to the electronic ceramic package substrate.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.1-12
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• 1998

We have implemented receiver for a 3 Dimensional Phased-Array Radar detecting the azimuth angle, the altitude, the range of a target on real time. This system consists of high frequency module, which protects receiver and controls sensitivity, intermediate frequency module, monopulse detector, IQ phase detector, AGC controller. A two-channel receiver with same function is implemented for increasing accuracy of target altitude data by amplitude comparison monopulse method. The TSS sensitivity of the receiver is -98dBm. The bandwidth of the receiver is 500 MHz. We can control the system gain manually by 100 dB when be AGC off. The gain and phase unbalance of two channels is 5 dB and 30 degree, respectively. The image rejection rate of the IQ detector is 30 dB. We used duroid substrate and package- type device.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.47-52
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• 2013

Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.185.2-185.2
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• 2014

We have studied the atomic and electronic structure of graphene nanoribbons (GNRs) on a hexagonal boron nitride (h-BN) sheet with intercalated atoms using first-principles calculations. The h-BN sheet is an insulator with the band gap about 6 eV and then it may a good candidate as a supporting dielectric substrate for graphene-based nanodevices. Especially, the h-BN sheet has the similar bond structure as graphene with a slightly longer lattice constant. For the computation, we use the Vienna ab initio simulation package (VASP). The generalized gradient approximation (GGA) in the form of the PBE-type parameterization is employed. The ions are described via the projector augmented wave potentials, and the cutoff energy for the plane-wave basis is set to 400 eV. To include weak van der Waals (vdW) interactions, we adopt the Grimme's DFT-D2 vdW correction based on a semi-empirical GGA-type theory. Our calculations reveal that the localized states appear at the zigzag edge of the GNR on the h-BN sheet due to the flat band of the zigzag edge at the Fermi level and the localized states rapidly decay into the bulk. The open-edged graphene with a large corrugation allows some space between graphene and h-BN sheet. Therefore, atoms or molecules can be intercalated between them. We have considered various types of atoms for intercalation. The atoms are initially placed at the edge of the GNR or inserted in between GNR and h-BN sheet to find the effect of intercalated atoms on the atomic and electronic structure of graphene. We find that the impurity atoms at the edge of GNR are more stable than in between GNR and h-BN sheet for all cases considered. The nickel atom has the lowest energy difference of ~0.2 eV, which means that it is relatively easy to intercalate the Ni atom in this structure. Finally, the magnetic properties of intercalated atoms between GNR and h-BN sheet are investigated.