• 전기학회논문지
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• 제57권6호
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• pp.1017-1021
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• 2008

A calculable potential transformer(PT) with nominal ratio error in wide range of -10% to +10% has been developed on basis of theoretical calculation of ratio error by the number of windings. The developed PT can be used to evaluate the linearity and accuracy of the PT comparator by comparing both the theoretical and experimental values of the PT which have exactly same ratio errors in nominal and calculated values. The PT has been applied for calibration and correction of the PT comparator up to wide ratio error range of -10% to +10%. This portable PT is very convenient to carry to the power industry for the on-site calibration of the PT comparator.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권6호
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• pp.317-322
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• 2006

A accurate potential transformer(PT) with the nominal ratio errors in the wide range of - 9 % to + 11 % has been developed. The developed wide ratio error PT can be used to evaluate the linearity of the PT comparator by comparing both the theoretical values as standard values and experimental values of the PT. The new method has been successfully applied for calibration and correction in the PT comparator including very low ratio error values from ${\pm}0.005%$ to ${\pm}0.3%$ belonging to industry.

• 한국산업정보학회논문지
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• 제20권1호
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1387_1388
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• 2009

High accurate and stable 132 kV potential transformers (PTs) including 66 kV & 22 kV PT with stability of less than 0.0033 % for 13 month and with ratio error within $\pm$ 0.024 % at full rated voltage have been developed. The PTs are useful as the reference PT of the PT comparator system in the voltage range of 11 kV to 132 kV PT.

• Journal of Electrical Engineering and Technology
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• 제2권3호
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• pp.401-407
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• 2007

Precise absolute measurement of the errors in a potential transformer (PT) can be achieved using high voltage capacitance bridge (HVCB) and capacitive divider. The uncertainty in a PT measurement using the HVCB system was evaluated by considering the overall factors affecting during the calibration of a PT. The expanded uncertainties are found to be not more than $30{\times}10^{-6}$ for ratio and $30{\mu}rad$ for phase up to the primary voltage of $V_p=22kV$. For same PTs, the measured errors in KRISS (Korea Research Institute of Standards and Science) using our bridge are well coincide with those in NMIA (National Measurement Institute of Australia) and PTB (Physikalisch-Technische Bundesanstalt) within the corresponding uncertainties.