• Title/Summary/Keyword: PSPICE

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High Power-Factor Single-Stage Half-Bridge High Frequency Resonant Inver (고역률을 가지는 Single-Stage Half-Bridge 고주파 공진 인버터)

  • Won, Jae-Sun;Kim, Dong-Hee;Seo, Cheol-Sik;Cho, Gyu-Pan;Oh, Seung-Hoon;Jung, Do-Young;Bae, Yeong-Ho
    • Proceedings of the KIEE Conference
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    • 2002.07b
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    • pp.1196-1198
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    • 2002
  • A novel single-stage half-bridge high frequency resonant inverter using ZVS(Zero Voltage Switching) with high input power factor suitable for induction heating applications is presented in this paper. The proposed high frequency resonant inverter integrates half-bridge boost rectifier as power factor corrector(PFC) and half-bridge resonant inverter into a single stage. The input stage of the half-bridge boost rectifier is working in discontinuous conduction mode (DCM) with constant duty cycle and variable switching frequency. So that a high power factor is achieved naturally. Simulation results through the Pspice have demonstrated the feasibility of the proposed inverter. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, DC-DC converter etc.

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A 1bit Carry Propagate Free Adder/Subtracter VLSI Using Adiabatic Dynamic CMOS Logic Circuit Technology

  • Takahashi, Yasuhiro;Yokoyama, Michio;Shouno, Kazuhiro;Mizumuma, Mitsuru;Takahashi, Kazukiyo
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.349-352
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    • 2002
  • This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

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Design for a New Signals Analyzer through the Circuit Modeling Simulation under Severe Accident Conditions (중대사고 조건에서 회로 모델링 모의시험을 통한 새로운 신호분기의 설계)

  • Koo, Kil-Mo;Kim, Sang-Baik;Kim, Hee-Dong;Kang, Hee-Young;Kang, Hae-Yong
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.171-174
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    • 2005
  • The circuit simulation analysis and diagnosis methods are used to instruments in detail when they give apparently abnormal readings. In this paper, a new simulator through an analysis of the important circuits modeling under severe accident conditions has been designed, the realization for a body work instead of the two sorts of the Labview & Pspice as an one order command in the Labview program. The program can be shown the output graph form the circuit modeling as an order commend. The procedure for the simulator design was divided into two design steps, of which the first step was the diagnosis methods, the second step was the circuit simulator for the signal processing tool. It has three main functions which are a signal processing tool, an accident management tool, and an additional guide from the initial screen.

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A Study on the CCFL Parallel Driving Circuit for the large LCD TV (대화면 LCD TV용 CCFL 병렬 구동에 관한 연구)

  • Jang, Young-Su;Yoon, Seok;Kweon, Gie-Hyoun;Han, Sang-Kyoo;Hong, Sung-Soo;Sakong, Suk-Chin;Roh, Chung-Wook
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.5
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    • pp.454-462
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    • 2006
  • To enhance the competitive edge of the material cost, various techniques lowering the material cost of inverter to drive Cold Cathode Fluorescent Lamp (CCFL) have been developed. In this paper, the theoretical analysis has been done for the existing techniques such as Jin Balance and O2Micro technique. Especially, How to design the value of magnetizing inductance to meet the specification of the lamp current tolerance between lamps has been disclosed. Based on this result, two kinds of hybrid type balancing techniques have been proposed and analyzed mathematically, Also, the accuracy of the proposed techniques has been verified through Pspice simulation.

A Study on the Novel Time Sharing Type Current Fad High Frequency Resonant Inverter (새로운 시분할 방식 전류형 고주파 인버터에 관한 연구)

  • Kim H.J.;Won J.S.;Kang J.W.;Cho G.P.;Oh S.H.;Min B.J.;Jung D.Y.
    • Proceedings of the KIPE Conference
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    • 2003.07a
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    • pp.27-30
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    • 2003
  • This paper describes two novel current fed high frequency resonant inverter can be used as the power supp]y for wax-sealing. This two topology can be obtained higher output frequency than switching frequency by composing modified unit inverter based on conventional half-bridge serial resonant inverter in parallel with input power source. also, By using time-sharing gate control method, this proposed inverter can not only realize the output control of dependence irrespective of the switching frequency using phase-shift but also reduce switching loss because it has ZVS function. Simulation results through the Pspice have demonstrated the feasibility of the proposed inverter. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, DC-DC converter etc.

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Design of a 1.2kW 14V Low Voltage Output High Efficiency Full-Bridge DC-DC Converter (1.2kW 14V 저전압 고효율 플-브릿지 DC-DC 컨버터 설계)

  • Jang, Dong-Wook;Kim, Hoon;Kim, Hee-Jun
    • Proceedings of the KIEE Conference
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    • 2008.10b
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    • pp.524-525
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    • 2008
  • 본 논문에서는 각각의 스위치 시비율(Duty ratio)의 변화를 이용한 기존의 풀-브릿지 방식과 두 쌍의 스위치 신호 위상 변화를 이용한 위상천이 풀-브리지(Phase-shift Full-bridge) 방식의 차이점을 서술하였다. 위상천이 컨버터의 안정성을 연구하기 위하여, 출력 전류의 맥동(ripple)을 작게 하는 배전류(Current Doubler) 정류회로와 효율을 높이기 위한 동기 정류기(Synchronous Rectifier)를 포함한 평균화 된 스위치 모델을 제안한다. 이 모델을 이용하여 PSPICE 시뮬레이션을 통해 안정성을 고찰하였으며 1.2kW급 170-14V DC-DC 컨버터의 시작품을 제작 후 시뮬레이션 결과와 시작품 결과를 비교하였다. 시뮬레이션의 경우 위상여유는 $58^{\circ}$ 시작품의 위상여유는 $68^{\circ}$로 나타났으며 교차주파수는 12kHz로 동일하게 나오는 것을 확인하였다. 따라서 제안한 시뮬레이션 모델을 이용하여 실제 회로의 안정성을 예측할 수 있으며 이를 실제 회로 제작에 활용 할 수 있다.

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Induction Voltage Adder for High Power Pulse Generator (유도전압합성기를 이용한 고전압 펄스발생기 설계)

  • Yang, Jong-Won;Shin, Jin-Woo;Ryu, Han-Young;Heo, Hoon;Lee, Woo-Sang;Kim, Chang-Gu;Nam, Sang Hoon;So, Joon-Ho
    • Journal of the Korea Institute of Military Science and Technology
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    • v.16 no.5
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    • pp.703-711
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    • 2013
  • In this paper, we have proposed high power generator with Induction Voltage Adder of three cells. IVA which has n cells can generate n-th times high power pulse, is a more stable system than Marx generator in the view of breakdown. We applied amorphous metal magnetic cores as an energy storing material for IVA rather than ferrite cores because of their higher magnetic flux swing to make it more compact system and the loss of it was also considered in the design. For driving the IVA, we design Blumlein pulse generators which are filled with pure water for high dielectric constant and high breakdown field strength, and triggered by single Marx generator. We have presented the PSPICE simulation and its test result.

Fast Partial Shading Analysis of Large-scale Photovoltaic Arrays via Tearing Method

  • Zhang, Mao;Zhong, Sunan;Zhang, Weiping
    • Journal of Power Electronics
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    • v.18 no.5
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    • pp.1489-1500
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    • 2018
  • Partial shading analysis of large-scale photovoltaic (PV) arrays has recently become a theoretically and numerically challenging issue, and it is necessary for PV system designers. The main contributions of this study are the following: 1) A PSIM-based macro-model was employed because it is remarkably fast, has high precision, and has no convergence issues. 2) Three types of equivalent macro-models were developed for the transformation of a small PV sub-array with uniform irradiance to a new macro-model. 3) On the basis of the proposed new macro-model, a tearing method was established, which can divide a large-scale PV array into several small sub-arrays to significantly improve the efficiency improvement of a simulation. 4) Three platforms, namely, PSIM, PSpice, and MATLAB, were applied to evaluate the proposed tearing method. The proposed models and methods were validated, and the value of this research was highlighted using an actual large-scale PV array with 2420 PV modules. Numerical simulation demonstrated that the tearing method can remarkably improve the simulation efficiency by approximately thousands of times, and the method obtained a precision of nearly 6.5%. It can provide a useful tool to design the optimal configuration of a PV array with a given shading pattern as much as possible.

A Analysis of DC Control Circuit Transient and a Study of Auxiliary Relay Design Compatability in the Power Plant (발전소 직류 제어회로 과도현상 분석 및 보조계전기 선정 적합성 검토)

  • Seon, Hyun-Gyu;Hong, Young-Hee
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1948_1949
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    • 2009
  • All the power generating station require dc auxiliary power systems to operate those dc components that must be available if a loss of ac power occur. Some examples of such components are auxiliary motors, circuit breakers, relays and solenoids. The dc source may be one common battery for both power and control or two separate batteries; one for power and another for control. Typically, a dc auxiliary power system is designed as an ungrounded system, instead of grounded system, so that a low-resistance ground fault on one of its two polarities will not affect the operation of the system, thus increasing system reliability and continuity of service. A ground detector should provide a high polarity-to-ground resistance so that a single ground fault occurring on the system will not affect the operation of that system. Sensitive relays have been known to energize momentarily while the cable and capacitive charge to ground shifts[1]. A power station had experienced this kind of incident and performed root cause analysis based on PC based simulation program known as PSpice. This simulation showed adapted relays on the system energize momentarily and design criteria on this relay should be corrected.

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The operational characteristics of the AT Forward Multi-Resonant Converter (AT 포워드 다중 공진형 컨버터의 동작 특성)

  • 김창선
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.12 no.3
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    • pp.114-123
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    • 1998
  • The multi-resonant converter(MRC) minimizes a parasitic oscillation by using the resonant tank circuit absorbed parasitic reactances existing in a converter circuit. So it si possible that the converter operated at a high frequency has a high efficiency because the losses are reduced. Such a MHz high frequency applications provide a high power density [W/inch3] of the converter. But the resonant voltage stress across a switch of the resonant tank circuit is 4~5 times a input voltage. This h호 voltage stress increases the conduction loss because of on-resistance of a MOSFET with higher rating. Thus, in this paper we proposed the alternated multi-resonant converter (AT MRC) differ from the clamp mode multi-resonant converter and applicated it to the forward MRC. The AT forward MRC can reduce the voltage stress to 2~3 times a input voltage by using two series input capacitor. The control circuit is simple because tow resonant switches are driven directly by the output pulse of the voltage controled oscillator. This circuit type is verified through the experimental converter with 48V input voltage, 5V/50W output voltage/power and PSpice simulation. the measured maximum voltage stress is 170V of 2.9 times the input voltage and the maximum efficiency of 81.66% is measured.

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