• Title/Summary/Keyword: PN code Acquisition

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Detection technique for code acquisition in DS-SS systems employing PN matched filters

  • 유영환;문태현;주판유;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.7
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    • pp.1699-1706
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    • 1998
  • This paper presents a threshold decision technique for direct sequence code acquistion employing Pseudo-Noise(PN) matched filter. The probabilities of detection and false alarm are derived as a measure of the system performance in both nonfading and nonselective Rician fading channels. For received PN codes with different SNR, the proposed acquisition scheme is able to detect a desired threshold in the search mode so that this value is utilized as a threshold for the verification mode. Thus, there is no need to determine a threshold by applying the Neyman-Person ciriteron. It is shown that this scheme achieves lower probability of false alarm than the acquisition scheme based on the Neyman-Person criterion, giving comparable performance in terms of the probability of detection.

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A FPGA implementation of a full-digital code acquisition/Tracking Loop for the CDMA direct-sequence spread-spectrum signals (대역 제한된 직접 시퀀스 CDMA 확산 대역 신호를 위한 전 디지탈 부호 획득 및 추적 루우프 FPGA 구현)

  • 김진천;박홍준;임형수;전경훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.5
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    • pp.165-171
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    • 1996
  • A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

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The design of the matched filter for CDMA rapid initial PN code synchronization acquisition using HW reuse scheme (CDMA 고속초기동기획득을 위한 HW 재사용에 의한 정합필터의 설계)

  • Lim, Myoung-Seob
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.11
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    • pp.28-36
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    • 1998
  • In the CDMA mobile communication system with asynchronous mode among base stations, the initial PN code acquisition method using a matched filter can be considered for the rapid PN code synchronization acquisition in the handoff region. In the model of the noncoherent QPSK/DS-SS under the Rayleigh fading channel, the mean acquisttion time of the matched filter is analyzed to have a shortened time in proportion to the length of matched filter to be compared with the serial correlation method. In this paper to improve the HW complexity of the conventional matched device which enables the repeated correlation process, is designed and its function is verified through the FPGAsimulation using Altera MaxPlus Ⅱ.

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Adaptive Filter Based PN Code Phase Acquisition Under Frequency Selective Rayleigh Fading Channels

  • Lee, Donghoon;Kim, Jeongchang;Cheun, Kyungwhoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.5
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    • pp.416-425
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    • 2013
  • A hybrid PN code phase acquisition system based on a least-mean-square adaptive filter, interpreted as a channel estimator is proposed and analyzed for direct-sequence spread-spectrum systems under frequency selective Rayleigh fading channels. Closed form expressions are derived for the filter tap weights and detection/false alarm probabilities. Compared to previously proposed systems, the proposed system achieves smaller mean acquisition times, is more robust to the operating signal-to-noise ratio and allows for multiplication free tap weight updates.

High speed matched filter synchronization circuit applied in frequency hopping FSK Transceiver (주파수도약 대역 확산 FSK 수신기의 고속 정합여파기 동기회로)

  • Kim, Seong-Cheol
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.8
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    • pp.1543-1548
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    • 2009
  • In this paper, a high speed code synchronization circuit is proposed. for fast code synchronization, matched filler method is used for initial code acquisition with two channel correlators. Particular frequency patterns of the limited number having the information about PN code start time are composed and transmitted repeatedly to increase the probability of accurate initial synchronization. And digital frequency synthesizer is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer.

Synchronization Scheme Using Phase Offsets of PN Sequences (PN 부호의 위상오프셋을 이용한 동기 방법)

  • Song, Young-Joon;Han, Young-Yearl
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2003.11a
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    • pp.581-584
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    • 2003
  • It is important to know phase offsets of PN (Pseudo Noise) sequences in spread spectrum communications since the acquisition is equivalent to make a phase offset between a receiving PN sequence and a PN sequence of local PN generator be identical. In this paper, a phase offset enumeration method for PN sequences with error detection, and its application to the synchronization are proposed. The phase offset enumeration far an n-tuple PN sequence and its error detection are performed when one period of the sequence is received. Once the phase offset of the receiving sequence is calculated, we can easily accomplish the synchronization by initializing shift registers of a local PN generator according to the phase offset value. The mean acquisition time of the proposed synchronization method is derived analytically, and we see that the method acquires very fast acquisition in the high SNR (Signal-to- Noise Ratio) environment.

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Phase-Shift-Network-Based Differential Sequential Estimation for Code Acquisition in CDMA Systems (CDMA 시스템에서 부호 획득을 위한 위상 변이 네트워크 기반의 차동 순차 추정 기법)

  • Chong, Da-Hae;Lee, Byeong-Yun;Kim, Sang-Hun;Joung, Young-Bin;Song, Iick-Ho;Yoon, Seok-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3A
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    • pp.281-289
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    • 2007
  • In this paper, a novel pseudo noise (PN) code acquisition scheme called the phase-shift-network-based differential sequential estimation (PDSE) is proposed, in the presence of data modulation in code division multiple access (CDMA) systems. The PDSE has even less complexity compared with that of the dual correlating sequential estimation (DCSE), and the reduction in complexity becomes more significant as the period of PN code increases. Numerical results demonstrate that the PDSE performs equivalently to the DCSE with less complexity.

Code Acquisition with Receive Diversity and Constant False Alarm Rate Schemes: 2. Nonhomogeneous Fading Circumstance (수신기 다양성과 일정 오경보 확률 방법을 쓴 부호획득: 2. 벼균질 감쇄 환경)

  • Kwon Hyoung-Moon;Kang Hyun-Gu;Park Ju-Ho;Ahn Tae-Hoon;Lee Sung-Ro;Song Iick-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.7C
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    • pp.725-734
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    • 2006
  • As a sequel to Part 1, the performance characteristics of the cell averaging (CA), greatest of (GO), and smallest of (SO) constant false alarm rate (CFAR) processors in nonhomogeneous environment are obtained and compared when receiving antenna diversity is employed in the pseudonoise (PN) code acquisition of direct-sequence code division multiple access (DS/CDMA) systems. Unlike in homogeneous environment, the GO CFAR processor is observed to exhibit the best performance in nonhomogeneous environment, with the CA CFAR processor performing the second best.

PN Chip Clock Generator for CDMA Code Synchronization

  • Oh, Hyun-Seo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.1 no.2
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    • pp.193-197
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    • 1997
  • In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

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Performance Analysis of Ranging Techniques for the KPLO Mission

  • Park, Sungjoon;Moon, Sangman
    • Journal of Astronomy and Space Sciences
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    • v.35 no.1
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    • pp.39-46
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    • 2018
  • In this study, the performance of ranging techniques for the Korea Pathfinder Lunar Orbiter (KPLO) space communication system is investigated. KPLO is the first lunar mission of Korea, and pseudo-noise (PN) ranging will be used to support the mission along with sequential ranging. We compared the performance of both ranging techniques using the criteria of accuracy, acquisition probability, and measurement time. First, we investigated the end-to-end accuracy error of a ranging technique incorporating all sources of errors such as from ground stations and the spacecraft communication system. This study demonstrates that increasing the clock frequency of the ranging system is not required when the dominant factor of accuracy error is independent of the thermal noise of the ranging technique being used in the system. Based on the understanding of ranging accuracy, the measurement time of PN and sequential ranging are further investigated and compared, while both techniques satisfied the accuracy and acquisition requirements. We demonstrated that PN ranging performed better than sequential ranging in the signal-to-noise ratio (SNR) regime where KPLO will be operating, and we found that the T2B (weighted-voting balanced Tausworthe, voting v = 2) code is the best choice among the PN codes available for the KPLO mission.