• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.49-54
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• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• ETRI Journal
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• v.30 no.4
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.179-184
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• 2016

The electrical load testing system developed from this study was designed to control rated-capacity-testing or variable-load-testing in an active and precise manner and save electric energy during testing, and also to convert the saved electric energy through the electrical load testing system to grid line. As for the device under testing, it was designed to be applied to not only transformer, rectifier, voltage regulator, inverter which require grid voltage source but, also applied to electric power, aerogenerator, photovoltaic, hybrid generator, battery, etc. which do not require grid voltage source. The system was designed to return the power consumed during the testing to the grid line by connecting the synchronizing pwm inverter circuit to the grid voltage source, and was also made to enable the being-tested system from disuse of approximately 93.4% energy when compared to the conventional load testing system which has used the passive resistor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.32-38
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• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.