• 한국전자파학회논문지
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• 제22권11호
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• pp.1117-1124
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• 2011

본 논문은 Ka 대역 밀리미터파 탐색기용 주파수 합성기 설계 및 제작에 대한 논문이다. 위상 잡음과 주파수 해상도 및 불요파 특성을 개선하고자 DDS를 이용한 하이브리드 방식으로 구현하였다. 제안된 주파수 합성기는 대역폭 1 GHz, 주파수 스위칭 시간은 9 ${\mu}s$ 이하, 불요파 특성 -68.9 dBc 이하, 위상 잡음 특성은 오프셋 100 kHz에서 -113.58 dBc/Hz, 평탄도는 ${\pm}$0.7 dB 이하로 측정되었다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.250-254
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• 2007

As photovoltaic(PV) power generation systems become more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive powers of the load and PV system are closely matched, islanding detection by passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop (DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment according to IEEE Std 929-2000 islanding test.

• 전자공학회논문지A
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• 제33A권11호
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.281-286
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• 2007

In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using $0.5{\mu}m$ SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider. $0.5{\mu}m$ SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.

• Journal of electromagnetic engineering and science
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• 제7권4호
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• pp.161-168
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• 2007

A fast correlative vector direction finding(CVDF) system using active dipole antenna array for mobile direction finding(DF) applications is presented. To develop the CVDF system, the main elements such as active dipole antenna, multi-channel direction finder, and search receiver are designed and analyzed. The active antenna is designed as composite structure to improve the filed strength sensitivity over the wide frequency range, and the multi-channel direction finder and search receiver are designed using DDS-based PLL with settling time of below 35 us to achieve short signal processing time. This system provides the capabilities of the high DF sensitivity over the wide frequency range and allows for high probability of intercept and accurate angle of arrival(AOA) estimation for agile signals. The design and performance analysis according to the external noise and modulation schemes of the CVDF system with five-element circular array are presented in detail.

• 한국전자파학회논문지
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• 제25권11호
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• pp.1190-1196
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• 2014

본 논문은 넓은 고도 범위와 낮은 측정 오차를 갖는 주파수 변조 연속파(FMCW) 레이더 고도계의 설계 방안을 제안한다. 측정 고도의 동적 범위를 줄이기 위해 전파 고도계의 송신 경로에 광 지연선을 적용하여 넓은 고도 범위를 얻을 수 있다. 송신 전력과 수신단 이득을 제어하여 또한 수신 전력의 동적 범위를 줄일 수 있다. 더불어, 직접 디지털 합성기를 사용하여 변조 선형성을 향상시키고, 기준 클럭 신호를 위상 고정 루프의 옵셋(offset) 주파수로 사용하여 위상잡음을 최소화함으로써 낮은 고도 측정오차를 갖는다.

• 대한기계학회논문집B
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• 제26권7호
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• pp.1039-1046
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• 2002

Co-flow axisymmetric laminar premixed flame of methane was used to study the influence of air temperature and $N_2$ addition on the flame structure, temperature field and emission characteristics. OH 2-D images and temperatures along the centerline were measured experimentally by PLIF and CARS techniques respectively to observe the influences of dilution and thermal effects of $N_2$ in the gas mixture. Also, the concentration of NOx was measured at each condition by gas analyser to see the suppression effect of N2 addition on NOx emissions. It was found that OH concentrations distribute widely as air temperature goes higher, while the effect of $N_2$ addition is not significant. But $N_2$ addition highly contributes to the flame front and NOx emissions which was argued to be due to the reduction of flame temperature. In accordance with experimental study, numerical simulation using CHEMKlN code was carried out to compare the temperature results with those acquired by CARS measurement, and we could find that there is good agreement between those results.

• Journal of Korean Neurosurgical Society
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• 제47권4호
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• pp.298-301
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• 2010

Degenerated conditions such as herniated disc or spinal stenosis are common etiologies of lumbar radiculopathy. Less common etiologies include spinal extradural cyst such as synovial cysts and ganglion cysts. Ganglion cyst of the posterior longitudinal ligament (PLL) of the spine is a rare entity that can result in classical sciatica. Posterior longitudinal ligament cyst has no continuity with the facet joint and has no epithelial lining. Two young male patients presented with unilateral sciatica and were found to have intraspinal cystic lesions causing lumbar radiculopathy. Magnetic resonance imaging demonstrated rounded, cystic lesions (i.e., hypointense on T1-but hyperintense on T2-weighted images) adjacent to minimally dehydrated, nonherniated disc spaces in both cases. These patients underwent posterior decompression and cysts were excised, and their sciatic symptoms were completely resolved. Histological examination showed typical features of ganglion cysts in these cases.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.512-517
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• 1998

In a matrix converter, input side and output side are coupled with each other through switching elements. Since disturbances on either side affect directly on the other side, it requires a high-speed on-line control system to compensate them. We proposed in previous papers a new control strategy and an on-line control circuit for a matrix converter. The control circuit could keep the output voltage at commanded value against fluctuation in the supply voltage. Furthermore wave forms of the output voltage and the input current were always kept sinusoidal. The switching pattern was generated by comparing modified voltage references with a carrier. The carrier was synchronized with the supply voltage using a PLL system, which made the control circuit complicated and costly. This paper discusses on the possibility of an asynchronized carrier. Experiment results show the input current distortion in case of asynchronous carrier is bigger than that of synchronous carrier. However, the deterioration can be minimized by increased carrier frequency.