• Journal of Power Electronics
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• v.18 no.3
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• pp.853-862
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• 2018

Frequency coupling in the phase domain is a recently reported phenomenon for phase locked loop (PLL) based three-phase grid-inverter systems. This paper investigates the mechanism and stabilization method for the frequency coupling to the stability of grid-inverter systems. Self and accompanying admittance models are employed to represent the frequency coupling characteristics of the inverter, and a small signal equivalent circuit of a grid-inverter system is set up to reveal the mechanism of the frequency coupling to the system stability. The analysis reveals that the equivalent inverter admittance is changed due to the frequency coupling of the inverter, and the system stability is affected. In the end, retuning the bandwidth of the phase locked loop is presented to stabilize the three-phase grid-inverter system. Experimental results are given to verify the analysis and the stabilization scheme.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.2
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• pp.78-85
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• 2002

We introduce a rotational decision-directed joint algorithm of blind equalization coupled with carrier recovery for 32-QAM demodulation with high symbol rate. The proposed carrier recovery, which we call a rotational decision-directed carrier recovery(RDDCR), removes the residual phase difference by rotating the decision boundary for the kth received symbol by the frequency detector output of the (k-1)th received symbol. Since the RDDCR includes the function of PLL loop filter by rotating the decision boundary, it gives a simpler demodulator structure. The rotational decision-directed blind equalization(RDDBE) with the rotated decision boundary based on the Stop-and-Go Algorithm(SGA) operated during tracking the frequency offset by the RDDCR and removes intersymbol interference due to multipaths and channel noise. Test results show that symbol error rate of $10^{-3}$ is obtained before the forward error correction when SNR equals 15dB with 150KHz of carrier frequency offset and two multipaths, which is the channel condition for 32-QAM receiver.

• Microbiology and Biotechnology Letters
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• v.22 no.5
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• pp.485-490
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• 1994

A restriction endonuclease, PsyI, has been isolated from Pseudomonas syringae pv. pha- seolicola, and its catalytic properties have been studied. This enzyme was purified through strepto- mycin sulfate and ammonium sulfate fractionation, phosphocellulose Pll, DEAE-cellulose, hydroxy- apatite and Sephadex G-100 column chromatography. It's molecular weight was about 50,000 dalton as determined by 7.5% polyacrylamide gel electrophoresis containing 0.1% SDS. In catalytic proper- ties, PsyI shows stable at wide ranges of pH between 7.0 and 10.0, of temperature between 30$\circ$C and 37$\circ$C, and its thermal stability is between 25$\circ$C, and 45$\circ$C, at the presence Of 10 mM MgCl$_{2}$-PsyI essentially require Na salt for enzyme reaction, is rather inhibited in the high Na salt concent- ration. The presence of 2-mercaptoethanol is absolutely required for the enzyme activity. This endonuclease, PsyI was determined to be an isoschizomer of SalI from the results of the restriction mapping and DNA sequencing.

• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1824-1827
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• 1998

A Laser Doppler Vibrometer(LDV) was developed using He-Ne laser as a light source. The heterodyne method was employed and its output signal was digitally processed with a $\mu$-processor and the result was displayed with LCD. The frequency shifted object beam(40 MHz) by a Bragg cell was focused on the surface of the moving target and the Doppler shifted reflected beam was recombined with reference beam at the fast photodetector to produce frequency modulated signal centered at 40 MHz. The signal from the detector was amplified and downconverted to intermediate frequency centered at 1 MHz after mixing process. The voltage output that was proportional to the velocity of the moving surface was obtained using PLL. With the same method, the fringe pattern signal of the moving surface is obtained. This fringe pattern signal is converted to TTL signal with ZCD(zero-crossing detector) and then counted to calculate the displacement due to the vibration, which is displayed with LCD. This LDV can be used to measure the resonant frequency of the electric equipments such as circuit breakers and transformers, of which resonant frequencies are changed when they are damaged.

• Proceedings of the IEEK Conference
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• summer
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• pp.23-26
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• 2004

Five-port reflectometer which consists of a ring with 5 arms (two inputs, three outputs) and three RF power detectors has been used as a vector network analyser, a demodulator in the homodyne receiver as well as in Phase Looked Loop (PLL) and so on. Calibration of five-port reflectometer is an important task. In this paper, we present a calibration method of five-port for a propagation channel sounder. The method is based on measurement of the phase differences between the three voltages at the five-port's outputs in order to determine the ratio of two input incident waves. The frequency channel sounder based on five-port is calibrated for each frequency from 2.2 GHz to 2.6 GHz with 1 MHz step. This method can also determine the absolute delays of each propagation path in the propagation channel. The calibration method is validated using measurement data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1153-1157
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• 2004

This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.12
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• pp.1848-1856
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• 2012

This paper proposes a new grid-tied power conditioning system for battery energy storage, which is composed of a 2-stage DC-DC converter and a PWM inverter. The 2-stage DC-DC converter is composed of an LLC resonant converter connected in cascade with a 2-quadrant hybrid-switching chopper. The LLC resonant converter operates in constant duty ratio, while the 2-quadrant hybrid-switching chopper operates in variable duty ratio for voltage regulation. The operation of proposed system was verified through theoretical analysis and computer simulations. Based on computer simulations, a hardware prototype was built and tested to confirm the technical feasibility of proposed system. The proposed system could have relatively higher efficiency and smaller size than the existing system.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1176-1189
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• 2016

In this paper, a novel quasi-direct power control (Q-DPC) scheme based on a resonant frequency adaptive proportional-resonant (PR) current controller with a variable frequency resonant phase locked loop (RPLL) is proposed, which can achieve a fast power response with a unity power factor. It can also adapt to variations of the generator frequency in T-type Three-level shaft synchronous generator (SSG) converters. The PR controller under the static α-β frame is designed to track ac signals and to avert the strong cross coupling under the rotating d-q frame. The fundamental frequency can be precisely acquired by a RPLL from the generator terminal voltage which is distorted by harmonics. Thus, the resonant frequency of the PR controller can be confirmed exactly with optimized performance. Based on an instantaneous power balance, the load power feed-forward is added to the power command to improve the anti-disturbance performance of the dc-link. Simulations based on MATLAB/Simulink and experimental results obtained from a 75kW prototype validate the correctness and effectiveness of the proposed control scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.7A
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• pp.935-942
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• 2000

In this paper, miniature voltage-controlled oscillator(VCO) for 1.6GHz PCS band is designed and implemented. Colpitts type LC resonating oscillator is designed with multilayer PCB and circuit parameters are optimized using the circuit simulator. Using the optimized design parameters, miniature VCO with 6X6X1.8mm3 (0.065cc)dimensions is fabricated and experimented. Developed VCO has -1.67dBm $\pm$0.5dBm output power level in52.5MHz tunung range, and has -99.33dBc/Hz phase noise performance at 10 KHz frequency offset.