• Archives of Pharmacal Research
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• v.13 no.2
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• pp.147-150
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• 1990

Methotrexate (MTX)-poly-L-lysine (PLL) conjugate was relatively stable in phosphate buffer of pH 7.4 and in plasma. However, liver homogenate accelerated the release of MTX from the conjugate. Pharmacokinetics and tissue distribution of MTX were compared after intramuscular injection of MTX (treatment I) and MTX-PLL conjugate (treatment II), 10 mg/kg as free MTX to rabbits. The peak concentration of MTX in treatment II were significantly lower than those in treatment I. The amount of MTX excreted in 24-hr urine was significantly reduced in treatment II and it suggested that MTX be more metabolized in treatment II than in treatment I. The amounts of MTX remaining in each organ after 24-hr of intramuscular injection were not significantly different in both treatments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.687-694
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• 1999

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.421-427
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• 2004

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 ㎓ is proposed. The proposed frequency synthesizer is composed of 2.9 ㎓ PLL chip, 2.9 ㎓ oscillator, and 5.8 ㎓ buffer amplifier The measured data shows a frequency Outing range of 290 ㎒, ranging from 5.65 to 5.94 ㎓ about 0.5 ㏈m of output power, and a phase noise of -107.67 ㏈c/㎐ at the 100 ㎑ offset frequency. All spurious signals including fundamental oscillation power(2.9 ㎓) are suppressed at least 15 ㏈c than the desired second harmonic signal.

• Journal of Electrical Engineering and Technology
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• v.7 no.3
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• pp.358-365
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• 2012

A new third harmonic injection circuit for light-emitting diode (LED) drivers is proposed to eliminate electrolytic capacitors and thereby extend the lifetime of LED drivers. When a third harmonic current is injected to the input current of the LED driver, the required capacitance of the driver can be reduced. The proposed circuit can control an injection ratio and has simple circuitry. The synchronous third harmonic is generated by a phase locked loop (PLL), a 1/3 counter, and op-amps and applied to a power factor correction circuit. Thus, the storage capacitor can install film capacitors instead of the electrolytic capacitor. The value of storage capacitance can be reduced to 78% compared to an input power factor of 100%. The proposed circuit is applied to the 80W prototype LED driver to experimentally verify the performances.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.697-699
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• 2017

A novel structure of phase locked loop (PLL) which has small size with D Flip-Flop and sub charge pump has been proposed. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.72-73
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• 2013

본 논문은 계통 연계형 인버터에서 LPN 필터를 이용한 계통 위상 추종 방법을 제안한다. 기존의 FFT를 이용한 계통 위상 추종 알고리즘의 한주기 평균 계산부를 LPN 필터로 대체하여 위상 추종 성능을 개선하였다. 기존의 FFT-PLL의 경우 SRF-PLL과 달리 별도의 PI 게인 튜닝이 필요 없으며, 고조파와 같은 노이즈에 강인한 특징을 가진다. 하지만 위상 이동시에 새로운 위상을 추종하기 위해서 한주기 소요된다. 따라서 본 논문에서는 LPN 필터를 사용하여 반주기 이내에 추종할 수 있도록 성능을 개선하였다. 제안된 위상 추종 전략의 타당성을 실험을 통하여 검증하였다.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3139-3141
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• 2000

전압제어 트랜스컨덕터를 설계하여 튜닝범 위가 넓은 Gm-C 대역통과 필터를 CMOS 공정으로 설계하였다 Gm-C 필터는 트랜스컨덕터와 캐패시터로 구성된 적분기를 기본으로 구현되고 있다. 따라서 트랜스 컨덕터는 출력단에 캐패시터를 연결하였을 때 이상적인적인 적분기의 특성에 가까울수록 필터의 특성이 좋아지고 PLL 구조의 튜닝이 용이해진다. 본 논문에서는 1:3이상의 범위에서 튜닝이 가능하고 PLL을 기본으로한 자동튜닝과 선형전압 튜닝을 조합하여 주파수 제어회로를 설계하였다.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.