• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.305-308
• /
• 2007

본 논문에서는 전력품질 향상용 전력전자기기의 제어에 중요한 정보인 전원의 위상각을 검출하는 기존의 방법들에 대해서 먼저 알아보고, 그 중 불평형한 전원단 전압조건에서도 정확한 위상각을 검출할 수 있는 전차원 상태관측기를 이용한 정상분 전압 추출 PLL(Phase Locked Loop) 방법을 제안한다. 제안된 PLL 방법은 기존의 전역 통과 필터(APF, All Pass Filter)를 이용한 정상분 전압추출기 대신 전차원 상태관측기를 사용함으로써 불평형사고 발생 시 과도상태 응답특성을 개선하였다. 기존의 정상분 전압 추출 PLL 방법과 본 논문에서 제안된 PLL 방법의 성능을 비교하기 위해, 전원단 전압에 불평형 사고 발생시 위상각을 검출하는 모의실험과 실험을 하였고, 이를 통해 기존의 전역 통과 필터를 이용한 정상분 전압 추출 PLL 방법보다 제안된 전차원 상태관측기를 이용한 정상분 전압 추출 PLL 방법의 과도상태 응답특성이 개선됨을 입증하였다.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.3
• /
• pp.270-275
• /
• 2017

This paper proposes a double-phase-locked-loop (PLL) to improve the performance of position estimation in hall sensor-based permanent magnet synchronous motor control. In hall sensor-based control, a PLL is normally used to estimate the rotor position. The proposed Double-PLL consists of two PLLs, including a reset type integrator. The motor control is more accurate and has better performance than conventional PLL, such as a small estimated position ripple. The validity of the proposed algorithm is verified by simulations and experiments.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.16 no.4
• /
• pp.309-316
• /
• 2011

A PLL system has widely used for synchronizing the grid voltage at the grid-connected inverter for supplying power from the PV generation systems. In this paper, a PLL algorithm without both the loop filter and PI controller is suggested for improving the performance of synchronization at the single-phase and three-phase grid connected inverters. In order that the output voltage of a phase detector in the PLL has only a dc voltage, and it approaches to 0 when the synchronization signal is locked to the grid voltage, the feedback signals are determined by using two-phase voltages. After the PLL system with a proportional controller is modelled with the small signal analysis, the stability and steady-state error are investigated. Through the simulation studies and experimental results, the performances of the proposed PLL algorithm are verified.

• Journal of IKEEE
• /
• v.26 no.4
• /
• pp.714-721
• /
• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.8
• /
• pp.1283-1291
• /
• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.2
• /
• pp.134-141
• /
• 2009

The new method is proposed to improve the dynamics of the phase angle detector during abrupt voltage dip caused by a grid fault. Usually, LPF(low pass filter) is used in the feedback loop of SRF(Synchronous Reference Frame) - PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. A better transient response can be obtained with the proposed design method for SRF-PLL by the analysis of linearized model of the PLL system including LPF. Furthermore, in the proposed method, the controller gain and LPF cut-off frequency are changed from normal value to transient value when the voltage disturbance is detected. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the experiment.

• Journal of Power Electronics
• /
• v.17 no.1
• /
• pp.262-271
• /
• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.9
• /
• pp.903-911
• /
• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.3
• /
• pp.53-59
• /
• 2000

A received signal in mobile communication environments exhibits variation in both amplitude and phase due to the multipath fading. Therefore we analyzed the performance of DS/CDMA(Direct Sequence/code Division Multiple Access) DPSK(Differential Phase Shift Keying) system for the variations of PLL(Phase Locked Loop) gain with Tikhonov probability density function, assuming that the phase difference between transmitter and receiver signals is phase error. As a result, it is discovered that the performance of system could be improved by the control of PLL gain in compared with the DPSK system which does not consider the phase error. If the PLL gain is 1dB, the difference of two systems is 4.8dB and 0.4dB at 7dB. and if 30dB, it coincides. From above, it

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.12
• /
• pp.28-34
• /
• 2011

In this paper, a PLL frequency synthesizer for RSSI applications is designed by phase noise analysis. Required synthesizer performance is achieved by optimizing the noise performance of PLL components and a loop transfer function, since its phase noise, lock time, and spur suppression capability are determined by the performance of loop components and loop filter characteristics. As an application example, a PLL frequency synthesizer for RSSI applications, which operates at the frequency of 2.288GHz, is designed using the phase noise analysis. The validity of the design technique is proved by experiments.