• Title/Summary/Keyword: PECVD oxide

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Thin Film Characterization on Refractive Index of PECVD SiO2 Thin Films

  • Woo Hyuck Kong;In Cheon Yoon;Seung Jae Lee;Yun Jeong Choi;Sang Jeen Hong
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.2
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    • pp.35-39
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    • 2023
  • Silicon oxide thin films have been deposited by plasma-enhanced chemical vapor deposition in SiH4 and N2O plasma along the variation of the gas flow ratio. Optical emission spectroscopy was employed to monitor the plasma and ellipsometry was employed to obtain refractive index of the deposited thin film. The atomic ratio of Si, O, and N in the film was obtained using XPS depth profiling. Fourier Transform Infrared Spectroscopy was used to analyze structures of the films. RI decreased with the increase in N2O/SiH4 gas flow ratio. We noticed the increase in the Si-O-Si bond angles as the N2O/SiH4 gas flow ratio increased, according to the analysis of the Si-O-Si stretching peak between 950 and 1,150 cm-1 in the wavenumber. We observed a correlation between the optical emission intensity ratio of (ISi+ISiH)/IO. The OES intensity ratio is also related with the measured refractive index and chemical composition ratio of the deposited thin film. Therefore, we report the added value of OES data analysis from the plasma related to the thin film characteristics in the PECVD process.

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Mechanism Study of Flowable Oxide Process for Sur-100nm Shallow Trench Isolation

  • Kim, Dae-Kyoung;Jang, Hae-Gyu;Lee, Hun;In, Ki-Chul;Choi, Doo-Hwan;Chae, Hee-Yeop
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.68-68
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    • 2011
  • As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

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Properties of IZTO Thin Films on Glass with Different Thickness of SiO2 Buffer Layer

  • Park, Jong-Chan;Kang, Seong-Jun;Yoon, Yung-Sup
    • Journal of the Korean Ceramic Society
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    • v.52 no.4
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    • pp.290-293
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    • 2015
  • The properties of the IZTO thin films on the glass were studied with a variation of the $SiO_2$ buffer layer thickness. $SiO_2$ buffer layers were deposited by plasma-enhanced chemical vapor deposition (PECVD) on the glass, and the In-Zn-Tin-Oxide (IZTO) thin films were deposited on the buffer layer by RF magnetron sputtering. All the IZTO thin films with the $SiO_2$ buffer layer are shown to be amorphous. Optimum $SiO_2$ buffer layer thickness was obtained through analyzing the structural, morphological, electrical, and optical properties of the IZTO thin films. As a result, the IZTO surface roughness is 0.273 nm with a sheet resistance of $25.32{\Omega}/sq$ and the average transmittance is 82.51% in the visible region, at a $SiO_2$ buffer layer thickness of 40 nm. The result indicates that the uniformity of surface and the properties of the IZTO thin film on the glass were improved by employing the $SiO_2$ buffer layer and the IZTO thin film can be applied well to the transparent conductive oxide for display devices.

Employing Al Etch Stop Layer for Nb-based SNS Josephson Junction Fabrication Process (Al 식각정지층을 이용한 Nb-based SNS 조셉슨 접합의 제조공정)

  • Choi, J.S.;Park, J.H.;Song, W.;Chong, Y.
    • Progress in Superconductivity
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    • v.12 no.2
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    • pp.114-117
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    • 2011
  • We report our efforts on the development of Nb-based non-hysteretic Josephson junction fabrication process for quantu device applications. By adopting and modifying the existing Nb-aluminum oxide tunnel junction process, we develop a process for non-hysteretic Josephson junction circuits using metal-silicide as metallic barrier material. We use sputter deposition of Nb and $MoSi_2$, PECVD deposition of silicon oxide as insulator material, and ICP-RIE for metal and oxide etch. The advantage of the metal-silicide barrier in the Nb junction process is that it can be etched in $SF_6$ RIE together with Nb electrode. In order to define a junction area precisely and uniformly, end-point detection for the RIE process is critical. In this paper, we employed thin Al layer for the etch stop, and optimized the etch condition. We have successfully demonstrated that the etch stop properties of the inserted Al layer give a uniform etch profile and a precise thickness control of the base electrode in Nb trilayer junctions.

Properties of IZTO Thin Films Deposited on PET Substrates with The SiO2 Buffer Layer

  • Park, Jong-Chan;Kang, Seong-Jun;Chang, Dong-Hoon;Yoon, Yung-Sup
    • Journal of the Korean Ceramic Society
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    • v.52 no.1
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    • pp.72-76
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    • 2015
  • 150-nm-thick In-Zn-Tin-Oxide (IZTO) films were deposited by RF magnetron sputtering after a 10 to 50-nm-thick $SiO_2$ buffer layer was deposited by plasma enhanced chemical vapor deposition (PECVD) on polyethylene terephthalate (PET) substrates. The electrical, structural, and optical properties of the IZTO/$SiO_2$/PET films were analyzed with respect to the thickness of the $SiO_2$ buffer layer. The mechanical properties were outstanding at a $SiO_2$ thickness of 50 nm, with a resistivity of $1.45{\times}10^{-3}{\Omega}-cm$, carrier concentration of $8.84{\times}10^{20}/cm^3$, hall mobility of $4.88cm^2/Vs$, and average IZTO surface roughness of 12.64 nm. Also, the transmittances were higher than 80%, and the structure of the IZTO films were amorphous, regardless of the $SiO_2$ thickness. These results indicate that these films are suitable for use as a transparent conductive oxide for transparency display devices.

A Study on Pre-bonding of 3C-SiC Wafers using CVD Oxide (CVD 절연막을 이용한 3C-SiC 기판의 초기직접접합에 관한 연구)

  • ;;Shigehiro Nishino
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.10
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    • pp.883-888
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    • 2002
  • SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECYD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of 5.3 kgf/cm$^2$to 15.5 kgf/cm$^2$.

Isolation Technologies for Single-crystalline Silicon MEMS Structures Using Trench Oxide (트렌치 산화막을 이용한 단결정실리콘 MEMS 구조물의 절연기술에 관한 연구)

  • Lee, Sang-Chul;Kim, Im-Jung;Kim, Jong-Pal;Park, Sang-Jun;Yi, Sang-Woo;Cho, Dong-Il
    • Journal of Sensor Science and Technology
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    • v.9 no.4
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    • pp.297-306
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    • 2000
  • To improve the performance of MEMS devices, fabricating single-crystalline silicon HARS (high aspect ratio structure) with thicknesses of up to several tens of micrometers has been an active research topic in recent years. However, achieving electrical isolation, which is required for actuating a structure or sensing an electrical signal, has been one of the main problems in single-crystalline silicon HARS fabrication technologies. In this paper, new isolation technologies using high aspect ratio oxide beams and sidewalls are developed to achieve electrical isolation between electrodes of single-crystalline silicon HARS. The developed isolation technologies use insulating oxide structural supports from either the structural sides or from the bottom. In this case because the trench oxide supports have a depth of several tens of ${\mu}m$, the effects of residual stress must be considered. In this paper, insulating supports are fabricated using PECVD TEOS films, the residual stress of the insulating supports is measured, and the effect of the residual stress on the structure is analyzed. It is shown using microresonators, that the developed isolation technologies can be effectively used for HARS using single-crystalline silicon.

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Process Optimization of PECVD SiO2 Thin Film Using SiH4/O2 Gas Mixture

  • Ha, Tae-Min;Son, Seung-Nam;Lee, Jun-Yong;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.434-435
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    • 2012
  • Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.

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A Study on the Bond Strength of BCB-bonded Wafers (BCB 수지로 본딩한 웨이퍼의 본딩 결합력에 관한 연구)

  • Kwon, Yongchai;Seok, Jongwon;Lu, Jian-Qiang;Cale, Timothy;Gutmann, Ronald
    • Korean Chemical Engineering Research
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    • v.45 no.5
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    • pp.479-486
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    • 2007
  • Four point bending is used to study the dependences of bond strength of benzocyclobutene(BCB) bonded wafers and BCB thickness, the use of an adhesion promoter, and the materials being bonded. The bond strength depends linearly on BCB thickness, due to the thickness-dependent contribution of the plastic dissipation energy of the BCB and thickness independence of BCB yield strength. The bond strength increases by about a factor of two with an adhesion promoter for both $2.6{\mu}m$ and $0.4{\mu}m$ thick BCB, because of the formation of covalent bonds between adhesion promoter and the surface of the bonded materials. The bond strength at the interface between a silicon wafer with deposited oxide and BCB is about a factor of three higher than that at the interface between a glass wafer and BCB. This difference in bond strength is attributed to the difference in Si-O bond density at the interfaces. At the interfaces between plasma enhanced chemical vapor deposited (PECVD) oxide coated silicon wafers and BCB, and between thermally grown oxide on silicon wafers and BCB, 12~13 and $15{\sim}16bonds/nm^2$ need to be broken. This corresponds to the observed bond energies, $G_0s$, of 18 and $22J/m^2$, respectively. Maximum 7~8 Si-O $bonds/nm^2$ are needed to explain the $5J/m^2$ at the interfaces between glass wafers and BCB.

Double Layer Anti-reflection Coating for Crystalline Si Solar Cell (결정질 실리콘 태양전지를 위한 이층 반사방지막 구조)

  • Park, Je Jun;Jeong, Myeong Sang;Kim, Jin Kuk;Lee, Hi-Deok;Kang, Min Gu;Song, Hee-eun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.1
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    • pp.73-79
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    • 2013
  • Crystalline silicon solar cells with $SiN_x/SiN_x$ and $SiN_x/SiO_x$ double layer anti-reflection coatings(ARC) were studied in this paper. Optimizing passivation effect and optical properties of $SiN_x$ and $SiO_x$ layer deposited by PECVD was performed prior to double layer application. When the refractive index (n) of silicon nitride was varied in range of 1.9~2.3, silicon wafer deposited with silicon nitride layer of 80 nm thickness and n= 2.2 showed the effective lifetime of $1,370{\mu}m$. Silicon nitride with n= 1.9 had the smallest extinction coefficient among these conditions. Silicon oxide layer with 110 nm thickness and n= 1.46 showed the extinction coefficient spectrum near to zero in the 300~1,100 nm region, similar to silicon nitride with n= 1.9. Thus silicon nitride with n= 1.9 and silicon oxide with n= 1.46 would be proper as the upper ARC layer with low extinction coefficient, and silicon nitride with n=2.2 as the lower layer with good passivation effect. As a result, the double layer AR coated silicon wafer showed lower surface reflection and so more light absorption, compared with $SiN_x$ single layer. With the completed solar cell with $SiN_x/SiN_x$ of n= 2.2/1.9 and $SiN_x/SiO_x$ of n= 2.2/1.46, the electrical characteristics was improved as ${\Delta}V_{oc}$= 3.7 mV, ${\Delta}_{sc}=0.11mA/cm^2$ and ${\Delta}V_{oc}$=5.2 mV, ${\Delta}J_{sc}=0.23mA/cm^2$, respectively. It led to the efficiency improvement as 0.1% and 0.23%.