• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2088-2090
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• 1997

This paper consists of the speed sensorless vector control of induction motors with the estimation of rotor resistance. In the application of variable-speed induction motor drives, if an inaccurate rotor resistance is used because the rotor resistance can change due to skin effects and temperature variables, it is difficult to achieve a collect field orientation. In this paper, to overcome these difficulties adaptive algorithm is designed for rotor resistance identification. The proposed adaptive algorithm for rotor resistance estimation in the synchronous reference frame is applied by sliding mode current controller satisfing persistent excitation(PE) condition. Adaptive flux observer is here used for the purpose of estimating rotor flux and speed in the speed sensorless scheme. Computer simulations are carried out to verify the validity of the proposed algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.373-385
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• 2021

To provide convenience and safety of drivers, the recent vehicles are being equipped with a number of electronic control units (ECUs). Multiple ECUs construct a network inside a vehicle to share information related to the vehicle's status; in addition, the CAN protocol is normally applied. As the modern vehicles provide highly convenient and safe services, it provides many types of attack surfaces; as a result, it makes them vulnerable to cyber attacks. The automotive IDS (Intrusion Detection System) is one of the promising techniques for securing vehicles. However, the existing methods for automotive IDS are able to analyze only periodic messages. If someone attacks on non-periodic messages, the existing methods are not able to properly detect the intrusion. In this paper, we present a method to detect intrusions including an attack using non-periodic messages. Moreover, we evaluate our method on the real vehicles, where we show that our method has 0% of FPR and 0% of FNR under our attack model.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.2
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• pp.215-221
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• 2006

This paper is concerned with the control of multiple nonlinearities included in a humanoid robot system. A humanoid robot has some problems such as the structural instability, which leads to consider the control of multiple nonlinearities caused by driver parts as well as gear reducer. Saturation and backlash are typical examples of nonlinearities in the system. The conventional algorithms of backlash control were fuzzy algorithm, disturbance observer and neural network, etc. However, it is not easy to control the system by employing only single algorithm since the system usually includes multiple nonlinearities. In this paper, a switching Pill is considered for a control of saturation and a dual feedback algorithm is proposed for a backlash control. To implement the above algorithms, the system identification is firstly performed for the minimization of the difference between the results of simulation and experiment, and then the switching Pill gains are determined using genetic algorithm with some heuristic approach. The performance of the switching Pill controller for saturation and the dual feedback for backlash control is investigated through the simulation. Finally, it is shown that the implemented control system has good results and can be applied to the real humanoid robot system ISHURO.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.