• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.639-647
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• 1990

Dynamic time warp(DTW) needs for interative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at the real time recognition design which enables large dictionary hardware realization using DTW algorithm. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. We have accomplisehd circuit design and verification for the MIN blocks, and performed MIN layout and DRC(design rule check) using 3um CMOS N-Well rule base.ing 3um CMOS N-Well rule base.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.543-552
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• 1994

Dynamic Time Warp(DTW) needs for iterative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at real time recognition design enables large dictionary hardware realization using DTW algorithm. The DTW PE cell separated into three large blocks. "MIN" is the one block for counting accumulated minimum distance. "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. Circuit design and verification about the three block have been accomplished, and performed layout '||'&'||' DRC(design rule check) using 1.2 m CMOS N-Well rule base.CMOS N-Well rule base.

• Journal of the Korean Society for Railway
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• v.12 no.6
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• pp.1043-1048
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• 2009

PES (Programmable Electronic System) is used by software development for the train control system. PES has been widely used in real world and consists of hardware, firmware and application software. The PES are easily apply to many applications because its implementation has high flexibility. Many safety critical functions are realized through software in safety critical system. Normally, it is difficult to detect failures for PES system because the PES is too sophisticated to identify sources of the failure. So, the reliability analysis is needed by using software fault tolerance techniques. Currently, there are the recovery block, distributed recovery block, N-version programming, N self-checking programming in fault tolerance techniques. In this paper, the models of recovery block and N-version programming in software fault tolerance techniques are suggested by using the Markov model. Also, the reliability in the train control system is analyzed through changing time. The fault occupancy rates of the program, adjustment test and voter are stationary. So, the relation between time and reliability is presented by using Matlab program. In the result of reliability, the reliability of recovery block is more high than N-version programming in case of the same number of substitution block.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.648-658
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• 1990

There are many methods for speed up counting in speech recongition. A multiple processing method is the one way to achieve the aim using systolic array. This arithmetic operation by the array is achieved pipelining skill. And the operation is multiprocessing by processing element(PE) that is incresing counting efficiencies. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculated these minimum distances, and "ABS" seeks for the absolut values to the total sum of local distances. We have accomplished circuit design and verification about the "ADD" and "ABS" blocks, and performed total layout '||'&'||' DRC(design rule check) using 3um CMOS N-Well rule base.le check) using 3$\mu$m CMOS N-Well rule base.

• Applied Chemistry for Engineering
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• v.24 no.6
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• pp.668-671
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• 2013

This paper describes activated carbon block filters prepared by extrusion for water purifier. The specific surface area of the activated carbon blocks affecting the properties of a polymer binder were investigated. Polyethylene (PE) particles were used as a binder polymer and the effect of particle sizes on changes in the specific surface area of activated carbon blocks in addition to the adsorption properties of chloride anion in the aqueous solution were investigated. The sizes and shapes of PE particles were measured using SEM. The specific surface area of activated carbon was $1186m^2/g$. The specific surface area of PE binder was $444m^2/g$ and $940m^2/g$ with the particle sizes of $200{\mu}m$ and $20{\mu}m$, respectively. In order to verify the performance of the filter, chlorine adsorption experiments were conducted.

• Journal of Ocean Engineering and Technology
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• v.27 no.4
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• pp.1-8
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• 2013

Many PE (pre-erection) blocks are supported by wooden, concrete, or steel supports when they are stocked in the outdoor areas of a shipyard. Their positions and numbers are planned on the basis of the workers' experience. Recently, many shipyards have been making PE blocks with various shapes and weight distributions because of the variety of ships and building technologies. Therefore, it is now necessary to deal with blocks that they have no experience with. We propose a method to conveniently and quickly evaluate the structural safety of PE block supports, without the need for special knowledge and technology related to structural analysis. This method can reduce the large number of man hours (MH) normally needed for the analysis. The three-dimensional grillage analysis is performed for a simplified grillage model of a PE block. For efficiency, the grillage model of the PE block is automatically built from its three-dimensional CAD model, and its weight is also automatically distributed on the grillage model. The integrated system has been comprehensively implemented to perform the grillage analysis for the reaction forces on block supports. This paper describes how to make a grillage model of a PE block and estimate the weight distribution of the block on this grillage model. These steps are verified by comparing the supports reaction forces to those of the 3D finite element analysis for the PE blocks that are provided by a shipyard.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Elastomers and Composites
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• v.44 no.3
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• pp.274-281
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• 2009

Nylon 6 and nylon elastomer were prepared by anionic polymerization route. Nylon elastomers, composed of hard segment of polyamide(PA) and soft segment of polyether(PE), were synthesized by use of TDI terminated polyol with caprolactam. The morphology of the electrospun webs of nylon and nylon elastomers, observed by FE-SEM, showed that the porous electrospun web was composed of nanofibers, whose diameter were in the range of 100 to 180 nm. Their behavior of melting and crystallization and the chemical structure of nylon elastomers were investigated by DSC and ATR FT-IR. Result of tensile testing indicated that nylon has higher tensile strength and lower elongation than nylon elastomers. Atmospheric plasma(APP) with $O_2$ and $N_2$ as reactive gas modified the surface of electrospun nylon and electrospun nylon elastomers allowing them higher hydrophilicity, while APP with $CH_4$ as reactive gas modified the surface of polymers allowing higher hydrophobicity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8A
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• pp.821-828
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• 2008

In this paper, we present an optimized design of RS(23,17) decoder for UWB, which uses the pipeline structured-modified Euclidean(PS-ME) algorithm. Firstly, the modified processing element(PE) block is presented in order to get rid of degree comparison circuits, registers and MUX at the final PE stage. Also, a degree computationless decoding algorithm is proposed, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. Additionally, we optimize Chien search algorithm, Forney algorithm, and FIFO size for UWB specification. Using Verilog HDL, the proposed decoder is implemented and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 17,628.