• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.399-402
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• 1999

In this paper, a new method for calculating capacitance in arbitrarily shape structure is Presented. This new approach based on divergence theorem of Gauss\`s law is acheive by Surface-Contacted Element(SCE) for Gaussian surface. To evaluate accurate capacitance value in nonuniform electric field. in two dimensional analysis the interpolation using the elements which contact one nod (PE: Point-Element) or two nod (FE: Face-Element) is employed. Because the elements contacted with surface are very small compared with total elements in analytic model, SCE method has shorter computing time to calculate capacitance. This proposed method is verified by comparing the simulated results with value obtained by analytic method.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1394-1397
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• 1993

A Fuzzy Microprocessor(FMP) is presented, which is suitable for real-time control applications. The features include high speed inference of maximum 114K FLIPS at 20MHz system clocks, capability of up to 128-rule construction, and handing of 8 input variables with 8-bit resolution. In order to realize these features, the fuzzifier circuit and the processing element(PE) are well optimized for LSI implementation. The chip fabricated in 1.2$\mu\textrm{m}$ CMOS technology contains 71K transistors in 82.8 $\textrm{mm}^2$ die size and is packaged in 100-pin plastic QFP.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2287-2289
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• 1999

In this paper, a new method for calculating capacitance in multi-electrode system with arbitrarily shape is presented. This new approach based on divergence theorem and Gauss's law is achieved by Surface-Contacted Element(SCE) for Gaussian surface. To evaluate capacitance in multi-electrode system, two dimensional finite element method using only the elements which is contacted one nod (PE: Point-Element) or two nod (FE: Face-Element) with surface is employed. The proposed SCE method has short computing time to calculate capacitance which is because it uses only SCE elements and needs one calculation loop while exiting FEM method in servral loops. This method is verified by application in calculating capacitance using potential detection device model which is composed with anode, cathode, and floating electrode.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.11-20
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• 1994

We propose two architectures using two dimensional systolic arrays for the DCT/DST/DHT. One decomposes the N-point DCT/DST/DHT into even-and odd-numbered frequency samples, and then computes them independently at the same time. In addition, the proposed architecture can be used for the IDCT/IDST/IDHT. Anogher is the modified version for the DHT/IDHT. Two proposed architectures generate outputs sequentially using real multiplications and additions. As compared to the conventional methods the proposed systolic arrays exhibit many advantages in terms of simplicity of the processing element (PE), latency, and throughput. Teh simulation results using VHDL, international standard language for hardware description, show the effectiveness of the proposed architecture.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• Journal of Welding and Joining
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• v.21 no.3
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• pp.58-67
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• 2003

In this study, the formation mechanism of discontinuities in the laser fusion zone of diamond saw blade was investigated. $CO_2$ laser weldings were conducted along the butt between Fe base sintered tip and carbon steel shank with sets of variable welding parameters. The effect of heat input on irregular humps, outer cavity, inner cavity and bond strengh was evaluated. The optimum heat input to have a proper humps was in the range of 10.4~$17.6kJm_{-1}$. With increasing heat input, both outer and inner cavities were reduced. The outer cavity was caused by insufficient refill of keyhole, while inner cavity was caused by trapping of bubble in molten metal. The bubble came from sintered tip and intensive vaporization at bottom tip of the keyhole. A gas formation and low melting point element vaporization were not occurred during welding. We could not find any relationship between bond strength and amount of discontinuities. Because the fracture were occurred in not only sintered tip but also carbon steel shank due to hardness distributions.