• Journal of the Semiconductor & Display Technology
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• v.12 no.2
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• pp.45-50
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• 2013

This paper focuses on the fundamental issues for improving the efficiency and throughput of the AC PDP (Plasma Display Panel) manufacturing. The properties of the MgO protective layer affect the PDP efficiency. Especially, the secondary electron emission efficiency was affected on the deposition rate of MgO during the evaporation. In this study, the deposition rate of 5 $\AA$/s has given the maximum efficiency value of 0.05 It is demonstrated that the impurity gases such as $H_2O$, $CO_2$, CO or $N_2$, and $O_2$ can be remained inside the PDP panel before sealing and the amount of the impurity gases decreased rapidly as the base vacuum level increased, especially near $10^{-5}$ torr. The fundamental solution in order to overcome these problems is the vacuum in-line sealing process from the MgO evaporation to the final sealing of the panel without breaking the vacuum. We have demonstrated this fundamental process technology and shown the feasibility. The firing voltage was reduced down to 285 V at the base vacuum value of $10^{-6}$ torr, whreras it was about 328 V at the base vacuum value of $10^{-3}$ torr.

• Journal of Information Display
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• v.2 no.2
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• pp.32-38
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• 2001

PDP(plasma display panel) represents the gray levels by the pulse number modulation technique that results in undesirable dynamic false contours on moving images. This paper proposes a LUT(Look-up table) based error diffusion algorithm for reduction of the dynamic false contours. A quantitative measure of the dynamic false contours is defined first. The measure of the dynamic false contours is calculated through simulation of every gray level combination of two consecutive frames. Based on the calculated measures, a modified gray level for a pair of gray levels of two consecutive frames is chosen to reduce the dynamic false contours. The chosen gray levels serve as contents of a gray level conversion LUT. Given a pair of gray levels of two consecutive frames, the gray level of current frame is modified based on the gray level conversion LUT. The new gray level is displayed on PDP. An error diffusion algorithm is, then, applied to compensate for the differences in the gray levels.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.704-708
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• 2004

Recently, many nation have released standard such as IEC 61000-3-2 and IEEE 59, which impose a limit on the harmonic current drawn by equipment connected to AC line in order to prevent the distortion of an AC Line. Therefore, Plasma Display Panel (PDP) which is highlightened in digital display device also has the Power Factor Correction (PFC) circuit to meet the harmonic requirements. In PDP power module, the conventional boost converter is usually used for the PFC circuit. However, it comes serious thermal problem on it's bridge diode due to heat of PDP, and therefore the system stability is not guaranteed. In this paper, the bridgeless boost converter, which is used for PFC circuit of the PDP power module, is designed and verified the possibility of the application in a practical product in a view of efficiency, component count, temperature and etc.

• Journal of Information Display
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• v.7 no.1
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• pp.30-34
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• 2006

A sub-field rearrangement driving method has been proposed to reduce a DFC (Dynamic False Contour) phenomenon in plasma display panels. The proposed driving method expresses 256 gray levels with 16 sub-fields, while conventional one uses only 8 sub-fields. Notwithstanding the increase in the number of sub-fields, the display time is similar to the conventional 8 sub-fields driving method by appropriate choosing selective writing and selective erasing for sub-fields.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.2 no.4
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• pp.21-31
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• 1988

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.9
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• pp.7-11
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• 2007

The objective of this study is to evaluate the characteristics of a newly proposed high-speed drive method for the gray scale display for high-resolution plasma display panels(PDP). In the experiment it was found that the characteristics of gray scale display are not closely affected by a priming period below 50[${\mu}s$], the width of the priming period, and that it can be driven stably from the brightest sub-field to the darkest sub-field even though a priming discharge is applied to the 1 TV-field only once. Moreover, from the experimental result, the gray scale pattern of 8-bit and 9 sub-fields was stably displayed in the experimental PDP with scan pulses having the pulse width of 0.7[${\mu}s$]. An address voltage margin of about 25[V] and a sustain voltage margin of about 10[V] was obtained.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.1
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• pp.46-54
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• 2002

Plasma Display Panel (PDP) is required to be both the determination of white point of each gray level and the inverse gamma correction since no-balanced RGB cell and linear property of PDP, respectively. However, these two methods cause degradation of grey level representation and undesirable false contour in the dark areas on PDP. In this paper, we implemented real time image processor of the proposed error diffusion algorithm and unsharp masking operation to protect the blurring image caused by the error diffusion. Experimental results showed drastic improvements of gray level representation and reduction of undesirable false contour.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.91-93
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• 2006

A new High Efficiency splitted sustaining driver for Plasma Display Panel (PDP) is proposed. The proposed circuit is suitable for the large screen PDP. The features of the proposed circuit are zen voltage switching (ZVS) of all main power switches, the reduction of reaction power loss for energy recovering, the stable light emission and simple structure.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.78-80
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• 2006

A new low-cost asymmetric current-fed energy-recovery circuit (ERC) for a plasma display panel (PDP) is proposed. LC resonant circuit biased by $V_s/2$ and composed of single switch is used as ERC on both sides of the PDP, slow discharging and fast charging times can be employed, and inductor currents are built up before the PDP is charged and discharged. Therefore, it features a low cost, fully charged/discharged PDP, zero voltage switching (ZVS), low electromagnetic interference (EMI), low current stress, no severe voltage notch, and high energy-recovery capability.

• Journal of Power Electronics
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• v.2 no.3
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• pp.189-198
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• 2002

New concept of energy recovery for plasma display panel (PDP) Is proposed. Different from conventional LC resonant sustaining drivers, the current built up before inverting the polarity of the panel electrodes is utilized to change the panel Polarity together with energy Previously charged in Panel capacitance. This operation Provides zero -voltage-switching of switches and reduction of EMI by rejecting the surge current when the sustain switches are turned on. The build-up current helps to reduce transition time of panel polarity and may produce more stable light waveforms. This method shows a desirable characteristic that the circuit loss is similar to that of series resonant type energy recovery circuit which is very effective method.