• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.125-132
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• 2015

PCI Express is high-speed point-to-point serial protocol, the system is designed by analysing loss and jitter through Eye Diagram. It is necessarily analyzing high speed serial signals when the PCI Express Gen3 which has 8Gbps physical signal speed is designed especially. This paper deals with topology extraction, channel analysis, extraction of s-parameters and system signal integrity simulation within transceiver buffer models through PCI Express Gen3 server connecting switch system design. Optimal parameters of transmitter buffer equalizer are found through solution space simulation of de-emphasis and preshoot parameters to compensate channel loss.

• Proceedings of the IEEK Conference
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• summer
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• pp.281-284
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• 2004

In this paper, a verification method and model for a PCI-Express device are described. PCI-Express technology is one of new I/O interconnection technologies which is intended to replace conventional PCI based technology, and is introduced by PCI-SIG in 2002. For a fast prototyping, a verification suite which includes a behavioral model and stimuli is needed before actual design is finished. And also it should be simple in structure and accurate enough to verify the design. In this paper, an Early Verification Suite (EVS) which complies with PCI-Express protocol is developed and tested.

• Journal of Information Processing Systems
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• v.13 no.1
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• pp.95-103
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• 2017

The PCI Express is a widely used system bus technology that connects the processor and the peripheral I/O devices. The PCI Express is nowadays regarded as a de facto standard in system area interconnection network. It has good characteristics in terms of high-speed, low power. In addition, PCI Express is becoming popular interconnection network technology as like Gigabit Ethernet, InfiniBand, and Myrinet which are extensively used in high-performance computing. In this paper, we designed and implemented a evaluation platform for interconnect network using PCI Express between two computing nodes. We make use of the non-transparent bridge (NTB) technology of PCI Express in order to isolate between the two subsystems. We constructed a testbed system and evaluated the performance on the testbed.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.1334-1336
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• 2003

On the basis of comprehensive analysis and summarization of the image fusion algorithms provided by PCI Geomatica software, deficiencies in image fusion processing functions of this software are put forwarded in this paper. This limitation could be improved by further developing PCI Geomatica on the user’ side. Five effective algorithms could be added into PCI Geomatica. In this paper, the detailed description of how to customize and further develop PCI Geomatica by using Microsoft Visual C++ 6.0, PCI SDK Kit and GDB technique is also given. Through this way, the remote sensing imagery fusion functions of PCI Geomatica software can be extended.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.41-44
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• 2003

In this paper, we propose design of PCI Express Physical Layer for IP. The proposed design is compatible with PCI Express Base specification Revision 1.0a. and supports only single Lane. The best feature of this design is that Physical Layer includes Power Management block. Therefor, the entire design of PCI Express component is simplified. In the near future, as optimizing this design and extending Lane, we will redesign Physical Layer.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2868-2870
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• 2000

Vision systems need to have high speed transfer methods for transferring large data. After PC accepts PCL, PCI becomes a more effective method for data translation. PCI substitutes previous ISA. This paper proposes an architecture of vision system and window driver based on PCI.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.69-72
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• 2003

The PCI Express spec introduces retry buffer in Data Link Layer For data integrity. But this buffer have some restrictions as buffer's usage. So we proposed effective management for retry buffer on PCI-Express interface. Proposed buffer management give increase performance and data integrity simultaneously.

• The Korean Journal of Nuclear Medicine
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• v.39 no.2
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• pp.114-117
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• 2005

As the indication of percutaneous coronary intervention (PCI) has expanded to the more difficult and complicated cases, frequent restenosis is still expected after PCI. According to AHA/ACC guideline of the present time, routine use of myocardial perfusion single photon emission tomography (SPECT) is not recommended after coronary intervention, but symptom itself or exercise EKG is not enough for the detection of restensis or for the prediction of event-free survival. In high risk and/or symptomatic subjects, direct coronary angiography is required myocardial perfusion SPECT could detect restenosis in 79% of the patients if performed 2 to 9 months after PCI. Reversible perfusion decrease in the myocardial perfusion SPECT is known to be the major prognostic indicator of major adrerse cardiac event in PCI patients and also the prognosis is benign in the patients without reversible perfusion decrease. Though the cumulated specificity is 79% in the literature and optimal timing of myocardial perfusion SPECT is in controversy, SPECT is recommended even in asymptomatic patients at 3 to 9 months after PCI. Considering the evidences recently reported in the literature, myocardial perfusion SPECT is useful for risk stratification and detection of coronary artery restenosis requiring re-intervention in the asymptomatic patients after PCI.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.370-380
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• 2003

A large RAID system may consist of several PCI bus segments since a PCI bus segment can connect only a limited number of disks. In this paver, PCI bus transactions in a RAID system are classified in terms of the initiator and the target of the transaction. Also, the data transfer time of each transaction type is analyzed. By using the analysis results, read and write performance of two RAID system configurations are formulated. From simulation of the RAID system using the DEVS formalism, performance of the configurations are evaluated and compared with the analytical results while changing various system parameters.

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.54-60
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• 2013

The need for high performance of on-board computer (OBC) is essential due to the growing requirements and diversified missions, and so OBC has been developed on the basis of the standard design and reconfigurable modularization in order to improve the utilization of OBC for different missions. The processor in OBC of next generation satellite which is currently developed by KARI is adopted the LEON2-FT/AT697F processor based SPARC v8 as main processor and controls various devices such as SpaceWire, MIL-STD-1553B and CAN through PCI on the standardized communication chips. This paper presents the architecture and design of system software for LEON2-FT processor based on PCI, and development of PCI software component. Also it describes the porting of VxWorks 6.5 for LEON2-FT and the test under the simulation environment for LEON2-FT and PCI with communication chips.