• 한국콘텐츠학회논문지
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• 제6권4호
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• pp.46-54
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• 2006

다수 대의 표면실장기를 포함한 PCB조립라인의 생산성 향상을 위한 방법을 제시한다. PCB조립시간의 단축을 위하여 각 실장기 별로 부품공급 피더의 배치 및 실장순서가 최적화 되어야 하며, 표면실장기들의 라인 밸런스를 위하여 부품 할당이 최적화 되어야 한다. 전체의 최적화 문제를 정수계획문제로 수식화하며, 전향경로문제와 후향경로 문제로 분할하여 구성한다. 클러스터링 알고리즘과 branch-and-bound 알고리즘을 사용하여 전향경로문제의 해를 구하며, 할당 알고리즘과 연결 알고리즘을 사용하여 후향경로 문제의 해를 구한다. 시뮬레이션 결과를 통하여 제안된 방법의 성능을 평가한다.

• 한국경영과학회:학술대회논문집
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• 대한산업공학회/한국경영과학회 1994년도 춘계공동학술대회논문집; 창원대학교; 08월 09일 Apr. 1994
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• pp.221-221
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• 1994

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.3022-3024
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• 2005

연성 PCB(flexible printed circuit board)는 현재 노트북 PC와 디지털 카메라등에 적용되며, 굴곡성이 강하고 소형화 및 조립에 용이하여 주로 기판 사이나주기판과 외부 커넥터사이에 데이터의 전송매체로써 널리 사용되는 핵심부품이다. 근래에 개발되는 PCB 기반의 고성능 신호처리회로들은 데이터 전송율이 수백 MHz에서 수 GHz에 이르고 있으며, 신호선과 유전체, 접지판의 구조적 특성에 따라서, 반사 효과와 같은 신호무결성 문제들이 파생되어 신호의 최대성능을 제한하게된다. 이에 따라 적절한 임피던스 제어를 통하여 고성능신호들의 왜곡을 상쇄시키는 기술이 중요하게 되었다. 본 논문에서는 연성 PCB 전송라인을 위한 임피던스 모델을 대상으로 각 모델의 주요 특징 및 정확성을 분석하였다. 연성 PCB의 전송라인은 보통 전통적인 마이크로스트립 라인의 특성 임피던스 모델에 비해 신호선의 너비가 크며, 이를 반영한 개선된 수학적 임피던스 모델들이 제안되어 있다. 따라서 본 논문은 기존의 마이크로스트립 전송라인과 연성 PCB 전송라인에 적합한 수학적 모델들을 이용하여 신호 무결성 문제를 모의할 수 있는 CAE(computer-aided engineering) 도구의 임피던스 측정 결과를 비교 및 분석하였다.

• 한국경영과학회지
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• 제22권1호
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• pp.25-49
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• 1997

Printed circuit board (PCB) assembly line configuration is characterized by very long set-up times and high work in process (WIP) inventory level. The scheduling method can significantly reduce the set-up times and WIP inventory level. Greedy sequence dependent scheduling (GSDS) method is proposed based on the current methods. The proposed method is compared with the current method in terms of three performance measures: line throughput, average WIP inventory level, and implementation complexity.

• 제어로봇시스템학회논문지
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• 제3권4호
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• pp.381-388
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• 1997

This paper proposes a heuristic algorithm to efficiently perform line balancing in the PCB assembly line including multiple surface mounters efficiently. Generally, the problems in line balancing are classified into two kinds. Firstly, is the determining of the minimum number of machines required for achieving the desired production rate. Secondly, is the assign of jobs to multiple machines in order to minimize the cycle time which is defined as a maximum among the working times of machines when the number of machines is fixed. In this paper, we deal with the latter. We consider a PCB assembly line, including the multiple surface mounters arranged serially as a target system. Also, the conveyor is assumed to move at a constant speed and have no buffer. Considering that the minimum number of machines required for the desired production rate is a discrete nonincreasing function which is inversely proportional to the cycle time, we propose an optimization algorithm for line balancing by using the binary search method. The algorithm is validated through computer simulation, the results of which show that their shapes coincide nearly with those of optimal line balancing efficiency graphs regardless of the number of components, the performance of surface mounters, and the structure of assembly line.

• 산업경영시스템학회지
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• 제33권4호
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• pp.138-144
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• 2010

This research deals with multiple Gantry-type assembly machines for the optimization of PCB assembly line. The automated assembly machine has 6 nozzles which can linearly move the X axis and the Y axis different from the turret type assembly machine. Each machine is optimized while considering the whole line balancing of three machines in assembly process simultaneously. Simulation models are developed using AutoMod for comparison study with single machine operation cases under various conditions such as types and total number of components to evaluate the proposed method.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.1237-1240
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• 1996

This paper proposes a heuristic algorithm for performing the line balancing of PCB assembly fine including multiple surface mounters efficiently. We consider a PCB assembly line including the multiple surface mounters arranged serially as a target system. We assume that the number of heads of surface mounters can be changed. Also, the conveyor is assumed to move at a constant speed and have no buffer. Considering the minimum number of machines required for the desired production rate is a discrete nonincreasing function which is inversely proportional to the cycle time, we propose an optimization algorithm for line balancing by using the binary search method. Also we propose an head-changing algorithm. The algorithms are validated through the computer simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2439-2441
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• 2002

SMT형 인쇄회로기판 조립라인에서 SMD의 조립상태를 검사하는 검사기를 위한 경로계획 알고리즘을 제안한다. 경로계획 알고리즘은 FOV 생성 최적화와 생성된 FOV의 순서 최적화에 의하여, 검사기의 선체 검사 시간의 단축을 목표로 한다. 본 논문에서는 검사기 경로계획 문제를 수학적으로 모델링하고, 전체 검사 단계를 FOV 생성 단계와 순서결정 단계의 계층적 구조로 구성한다. 각 단계의 알고리즘은 FOV 생성 알고리즘과 TSP 알고리즘을 적용하여 구현한다. 제시된 알고리즘을 실제 검사장비에 적용하여 시뮬레이션하고, 그 유용성을 검증한다.

• 산업공학
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• 제23권1호
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• pp.58-67
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• 2010

The purpose of this paper is to present the development processes of the assembly line tester of power transmission for lift truck. Because power transmission is most important part of lift truck, all assembled powertrain parts must be inspected for operational defects, pressures and RPM. Developed assembly line tester is designed to take about 25 minutes for inspecting each assembled power transmission and located it at the end of assembled line. The assembly line no-load tester consists of three parts: (1) the driving hardware part; for installing and operating the transmission. (2) control PCB part; send data from sensors to a computer and control driving part, (3) operation software of no-load tester; for an automatic inspection or manual inspection, for database management and printing transcripts.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권4호
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.