• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.393-398
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• 2014

A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.34-38
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• 2010

In this paper, we suggest DCU(Digital Control Unit) for performance improvement and stability security of base station power amplifier. The designed DCU controls electric power that is supplied to power amplifier. When the regular input is 10dBm, the regular output is measured 47.8dBm and the results are compared between the case of the applying and the non-applying the DCU. We got the result that PA system is very stable as DCU are very well operating in the boundary degradation of IMD by the over-power level input.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.4
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• pp.286-297
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• 2017

This paper is a study of 6~18 GHz wideband high power amplifier which is composed of 10 single amplifier and coaxial type spatial power combiner. The property of this spatial power combiner is on a similar principle to antipodal antenna radiation mechanism. Therefore, the key structure of proposed spatial power combiner is the antipodal finline PCB board and the finline curve shape is numerically synthesized by using Klopfensein's optimum impedance taper. The measured CW output power of spatial combined high power amplifier is nearly 50 W. In conclusion we prove the good combining performance between the spatial power combiner and 10 single amplifier over 6~18 GHz frequency ranges. Also, we developed the key component PA and MFC MMIC which controls the phase and gain of the each amplifier, The main characteristic of MFC MMIC is to maximize combining efficiency of power amplifier.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.945-952
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• 2015

Power amplification device which is matched to $50{\Omega}$ in order to achieve a high efficiency of a power amplifier using a GaN power amplification device, since there is a limit of application frequency bands, output power, efficiency characteristics selection, in this study based on the measurement data through the source/load-pull test, high output power and to extract quantitative input and output impedance that matches the design objectives of high output power, high efficiency, an implementation of the high efficiency power amplifier. Implemented power amplifier is shows 25watt(44dBm), PAE of 66-76% characteristics in the frequency band of 2.7-3.1 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.48-58
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• 2012

New digital predistortion technique is proposed for power amplifier linearization in multi-band transmission systems. We consider a system where muli-band signals are combined and amplified by a single power amplifier (PA). In this system, the PA output is distorted by the nonlinear cross-products between different band signals as well as their own nonlinear self-products. To compensate these nonlinear effects, we propose a multiple PD structure. Each PD removes the nonlinear cross-products and self-products to mitigate the spectral regrowth for the corresponding band. Since the PD parameters for different bands are linked together, it is difficult to find the PD parameters separately. Thus, we propose an iterative method for finding the PD parameters jointly. For demonstration of the proposed method, multi-band characteristics of PA are extracted from a commercial power amplifier. Computer simulation was executed based on the PA parameters. The simulation results show that the proposed method can effectively linearize the PA and remove spectral regrowth at each signal band.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.261-264
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• 2004

In this paper, we identify the memory effect of high power(125W) laterally diffused metal oxide-semiconductor(LDMOS) RF Power Amplifier(PA) by two tone IMD measurement. We measure two tone IMD by changing the tone spacing and the power level. Different asymmetric IMD is founded at different center frequency measurements. We propose the Tapped Delay Line-Neural Network(TDNN) technique as the modeling method of LDMOS PA based on two tone IMD data. TDNN's modeling accuracy is highly reasonable compared to the memoryless adaptive modeling method.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.400-403
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• 2007

This research describes how the class D amplifiers with power efficiency are designed and implemented for the PA audio systems. The configuration that makes use of the class D amplifier properties depends strongly on their applications. Thus in this paper the characteristics of the 2-level and 3-level PWM are analysed and the circuit implementation for them is presented. Using the proposed methods, they are designed and simulated for the further investigation. Test(Simulation) results present the improved performance that shows the satisfactory operations in controlling the PWM to the input signals.

• Journal of electromagnetic engineering and science
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• v.14 no.2
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• pp.68-73
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• 2014

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

• ETRI Journal
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• v.31 no.5
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• pp.601-603
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• 2009

This letter presents a high performance 2.4 GHz two-stage power amplifier (PA) operating in the temperature range from $-30^{\circ}C$ to $+85^{\circ}C$ for IEEE 802.11g, wireless local area network application. It is implemented in InGaP/GaAs hetero-junction bipolar transistor technology and has a bias circuit employing a temperature compensation technique for error vector magnitude (EVM) performance. The technique uses a resistor made with a base layer of HBT. The design improves EVM performance in cold temperatures by increasing current. The implemented PA has a dynamic EVM of less than 4%, a gain of over 26 dB, and a current less than 130 mA below the output power of 19 dBm across the temperature range from $-30^{\circ}C$ to $+85^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.1
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• pp.102-106
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• 2009

This paper presents the design and optimization of output matching network according to envelope for class F power amplifier(PA) which is to apply to envelope elimination and restoration(EER) transmitter. In this paper, to increase the PAE of class F power amplifier which applies to EER transmitter, the varactor diode has been used on output matching network. As envelope changes, it optimizes constitution of harmonic trap that is short circuit in 2nd-harmonic and is open circuit in 3rd-harmonic. When drain voltage changes from 25 V to 30 V, some percentage is improved in the PAE.put the abstract of paper here.