• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.11
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• pp.720-724
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• 2016

Transparent n-type metal-oxide semiconductor of $MoO_x$ was applied on a p-type Si substrate for high-performing heterojunction photodetector. The formation of $MoO_x$ on Si spontaneously established a rectifying current flow with a high rectification ratio of 1,252.3%. Under light illumination condition, n-type $MoO_x$/p-type Si heterojunction device provided significantly fast responses (rise time : 61.28 ms, fall time : 66.26 ms). This transparent metal-oxide layer ($MoO_x$) would provide a functional route for various photoelectric devices, including photodetectors and solar cells.

• Proceedings of the Korean Ceranic Society Conference
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• 2000.10a
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• pp.158.1-158
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• 2000

• Proceedings of the Korean Ceranic Society Conference
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• 2002.10a
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• pp.34.1-34
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• 2002

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.91-95
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• 2012

ZnO thin films were deposited on p-type 4H-SiC substrate by pulsed laser deposition. ZnO nanowires were formed on p-type 4H-SiC substrate by furnace. Ti/Au electrodes were deposited on ZnO thin film/SiC and ZnO nanowire/SiC structures, respectively. Structural and crystallographical properties of the fabricated ZnO thin film/SiC and ZnO nanowire/SiC structures were investigated by field emission scanning electron microscope and X-ray diffraction. In this work, resistance and sensitivity of ZnO thin film/SiC gas sensor and ZnO nanowire/SiC gas sensor were measured at $300^{\circ}C$ with various CO gas concentrations (0%, 90%, 70%, and 50%). Resistance of gas sensor decreases at CO gas atmosphere. Sensitivity of ZnO nanowire/SiC gas sensor is twice as big as sensitivity of ZnO thin film/SiC gas sensor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.448-449
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• 2008

HIT(Heterojunction with intrinsic thin layer) solar cell은 결정 실리콘 (c-Si)을 n-type으로 제작시 수율이 어렵고 결정 실리콘 (c-Si)을 p-type위에 제조하는 것이 보다 보편적인 방법이므로 베이스의 결정 실리콘에는 p-type을, 그 위에는 진성 층(intrinsic layer) 그리고 반투명 전극의 아래에 제조되는 비정질 실리콘 (a-Si)을 n-type으로 하여 베이스 층과 TCO 후면 층의 두께, 도핑 농도 (doping concentration)와의 관계를 확인하여 본다.

• Journal of Sensor Science and Technology
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• v.7 no.6
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• pp.426-431
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• 1998

This paper describes electrochemical etch-stop characteristics in THAH/IPA/pyrazine solution. I-V curves of n- and p-type Si in THAH/IPA/pyrazine solution were obtained. OCP(Open Circuit Potential) and PP (Passivation Potential) of p-type Si were -1.2 V and 0.1 V, and of n-type Si were -1.3 V and -0.2 V, respectively. Both n- and p-type Si, etching rates were abruptly decreased at potentials anodic to the PP. The etch-stop characteristics in THAH/IPA/pyrazine solution were observed. Since accurate etching stop occurs at pn junction, Si diaphragms having thickness of epi-layer were fabricated. Etching rate is highest at optimum etching condition, TMAH 25wt.%/IPA 17vol.%/pyrazine 0.1g/100ml. thus the elapsed time of etch-stop was reduced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.94-94
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• 2008

We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.196-200
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• 2005

In this work, we investigated simple Aㅣ/TCO/a-Si:H(n)/c-Si(p)/Al hetero-junction solar cells prepared by low temperature processes, unlike conventional thermal diffused c-Si solar cells. a-Si:H/c-Si hetero-junction solar cells are processed by low temperature deposition of n-type hydrogenated amorphous silicon (a-Si:H) films by plasma-enhanced chemical vapor deposition on textured and flat p-type silicon substrate. A detailed investigation was carried out to acquire optimization and compatibility of amorphous layer, TCO (ZnO:Al) layer depositions by changing the plasma process parameters. As front TCO and back contact, ZnO:Al and AI were deposited by rf magnetron sputtering and e-beam evaporation, respectively. The photovoltaic conversion efficiency under AMI.5 and the quantum efficiency on $1cm^2$ sample have been reported. An efficiency of $12.5\%$ is achieved on hetero-structure solar cells based on p-type crystalline silicon.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.65-71
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• 1980

The Sn O2-Si Heterojunction sola cells are Prepared by vacuum deposition of SnO2 on N- and P-type Si - wafers arts the effects of annealing on the Solar cell characteiistics are presented. The existence of optimumannealins temperature for maximum open-circuit voltage and short - circuit current of the solar cell is observed. The optimum tomperature, when low resistivity (7- 2.3 [$\Omega$.cm]) P-and N-type Si -wafers are used, is 500 [$^{\circ}C$] End 400 [$^{\circ}C$] when high resistivity[41-58 [$\Omega$.cm]) P-type Si-wafers are used.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.40-46
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• 2018

In this paper, we focus on optimization of a boron ($^{11}B$)-implanted n type Si epi substrate for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $125^{\circ}C$. The $^{11}B$-implantation on the N type-Si epi substrate formed isolation from the rest of the N-type Si by the depletion region of a PN junction. The TCR increased as the temperature of rapid thermal anneal (RTA) was increased at the temperature range from $900^{\circ}C$ to $1000^{\circ}C$ for the $p^+$ contact with implantation at dose of $1E16/cm^2$, but sheet resistance of this film was decreased. After the optimization of anneal process condition, the TCR of $1126.7{\pm}30.3$ (ppm/K) was obtained for the $p^-$ resistor-COB package chips contained $p^+$ contact with the implantation of $5E14/cm^2$. This shows the potential of the $^{11}B$-implanted n type Si epi substrate as a resistor for pressure sensor in thermal stable environment applications..