• 제목/요약/키워드: P-type Si

검색결과 952건 처리시간 0.034초

Effect of p-type a-SiO:H buffer layer at the interface of TCO and p-type layer in hydrogenated amorphous silicon solar cells

  • Kim, Youngkuk;Iftiquar, S.M.;Park, Jinjoo;Lee, Jeongchul;Yi, Junsin
    • Journal of Ceramic Processing Research
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    • 제13권spc2호
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    • pp.336-340
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    • 2012
  • Wide band gap p-type hydrogenated amorphous silicon oxide (a-SiO:H) buffer layer has been used at the interface of transparent conductive oxide (TCO) and hydrogenated amorphous silicon (a-Si:H) p-type layer of a p-i-n type a-Si:H solar cell. Introduction of 5 nm thick buffer layer improves in blue response of the cell along with 0.5% enhancement of photovoltaic conversion efficiency (η). The cells with buffer layer show higher open circuit voltage (Voc), fill factor (FF), short circuit current density (Jsc) and improved blue response with respect to the cell without buffer layer.

N-Type c-Si 이종접합 태양전지 제작을 위한 a-Si:H(p) 가변 최적화 (A Study of Optimization a-Si:H(p) for n-type c-Si Heterojunction Solar Cell)

  • 허종규;윤기찬;최형욱;이영석;;김영국;이준신
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2009년도 춘계학술대회 논문집
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    • pp.77-79
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    • 2009
  • Amorphous/crystalline silicon heterojunction solar cells, TCO/a-Si:H (p)/c-Si(n)/a-Si:H(n)/Al, are investigated. The influence of various parameters for the front structures was studied. We used thin (10 nm) a-Si:H(p) layers of amorphous hydrogenated silicon are deposited on top of a thick ($500{\mu}m$) crystalline c-Si wafer. This work deals with the influence of the a-Si:H(p) doping concentration on the solar cell performance is studied.

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Hysteresis Characteristics in Low Temperature Poly-Si Thin Film Transistors

  • Chung, Hoon-Ju;Kim, Dae-Hwan;Kim, Byeong-Koo
    • Journal of Information Display
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    • 제6권4호
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    • pp.6-10
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    • 2005
  • The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.

p형 Si(100) 기판 상에 안티몬 도핑된 n형 Si박막 구조를 갖는 pn 다이오드 제작 및 특성 (Fabrication and Properties of pn Diodes with Antimony-doped n-type Si Thin Film Structures on p-type Si (100) Substrates)

  • 김광호
    • 반도체디스플레이기술학회지
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    • 제16권2호
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    • pp.39-43
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    • 2017
  • It was confirmed that the silicon thin films fabricated on the p-Si (100) substrates by using DIPAS (DiIsoPropylAminoSilane) and TDMA-Sb (Tris-DiMethylAminoAntimony) sources by RPCVD method were amorphous and n-type silicon. The fabricated amorphous n-type silicon films had electron carrier concentrations and electron mobilities ranged from $6.83{\times}10^{18}cm^{-3}$ to $1.27{\times}10^{19}cm^{-3}$ and from 62 to $89cm^2/V{\cdot}s$, respectively. The ideality factor of the pn junction diode fabricated on the p-Si (100) substrate was about 1.19 and the efficiency of the fabricated pn solar cell was 10.87%.

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낮은 접촉저항을 갖는 Ni/Si/Ni n형 4H-SiC의 오옴성 접합 (Low Resistivity Ohmic Ni/Si/Ni Contacts to N-Type 4H-SiC)

  • 김창교;양성준;조남인;유홍진
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제53권10호
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    • pp.495-499
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    • 2004
  • Characteristics of ohmic Ni/Si/Ni contacts to n-type 4H-SiC are investigated systematically. The ohmic contacts were formed by annealing Ni/Si/Ni sputtered sequentially The annealings were performed at 950℃ using RTP in vacuum ambient and N₂ ambient, respectively. The specific contact resistivity(p/sub c/), sheet resistance(R/sub s/), contact resistance (R/sub c/) transfer length(L/sub T/) were calculated from resistance(R/sub T/) versus contact spacing(d) measurements obtained from TLM(transmission line method) structure. While the resulting measurement values of sample annealed at vacuum ambient were p/sub c/ = 3.8×10/sup -5/Ω㎠, R/sub c/ = 4.9 Ω and R/sub T/ = 9.8 Ω, those of sample annealed at N₂ ambient were p/sub c/ = 2.29×10/sup -4/Ω㎠, R/sub c/ = 12.9 Ω and R/sub T/ = 25.8 Ω. The physical properties of contacts were examined using XRD 3nd AES. The results showed that nickel silicide was formed on SiC and Ni was migrated into SiC. This result indicates that Ni/Si/Ni ohmic contact would be useful in high performance electronic devices.

CVD로 성장된 다결정 3C-SiC 박막의 전기적 특성

  • 안정학;정귀상
    • 한국반도체및디스플레이장비학회:학술대회논문집
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    • 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
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    • pp.179-182
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    • 2007
  • Polycrystaline (poly) 3C-SiC thin film on n-type and p-type Si were deposited by APCVD using HMDS, $H_2$, and Ar gas at $1180^{\circ}C$ for 3 hour. And then the schottky diode with Au/poly 3C-Sic/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) value were measured as 0.84 V, over 140 V, 61nm, and $2.7{\times}10^{19}\;cm^3$, respectively. The p-n junction diode fabricated by poly 3C-SiC was obtained like characteristics of single 3C-SiC p-n junction diode. Therefore, its poly 3C-SiC thin films are suitable MEMS applications in conjuction with Si fabrication technology.

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변형 힘을 받는 p형 $Si_{1-x}Ge_x$의 이동도 연구 (Study of the Mobility for Strained p-type $Si_{1-x}Ge_x$ Alloys)

  • 전상국
    • 한국전기전자재료학회논문지
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    • 제11권3호
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    • pp.181-187
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    • 1998
  • The ionization energy and degree of ionization for p-type $Si_{1-x}Ge_x$ with boron doping are calculated taking into account the screening and broadening effects. The drift and Hall mobilities are then calculated using the relaxation time approximation and compared with the previously reported measurement data for relaxed and strained $Si_{1-x}Ge_x$ alloys to estimate the alloy scattering potential. From a fit, the alloy scattering potential is found to be 0.5 eV. The in-plane drift mobility for p-type strained $Si_{1-x}Ge_x$ grown on (001) Si substrate is approximately 1+$10x^2$ times higher than that for bulk Si in the high doping range.

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P형 실리콘 나노선과 Au 나노입자를 이용한 나노플로팅게이트 메모리소자의 전기적 특성 분석 (Memory characteristics of p-type Si nanowire - Au nanoparticles nano floating gate memory device)

  • 윤창준;염동혁;강정민;정동영;김상식
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.1226-1227
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    • 2008
  • In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

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PL Property of Al-N Codoped p-type ZnO Thin Films Fabricated by DC Magnetron Sputtering

  • Liu, Yan-Yan;Jin, Hu-Jie;Park, Choon-Bae;Hoang, Geun-C.
    • Transactions on Electrical and Electronic Materials
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    • 제10권3호
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    • pp.89-92
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    • 2009
  • High-quality Al-N doped p-type ZnO thin films were deposited on Si and buffer layer/Si by DC magnetron sputtering in a mixture of $N_2$ and $O_2$ gas. The target was ceramic ZnO mixed with $Al_2O_3$ (2 wt%). The p-type ZnO thin films showed a carrier concentration in the range of $1.5{\times}10^{15}{\sim}2.93{\times}10^{17}\;cm^{-3}$, resistivity in the range of 131.2${\sim}$2.864 ${\Omega}cm$, mobility in the range of 3.99${\sim}$31.6 $cm^2V^{-1}s^{-l}$, respectively. It was easier to dope p-type ZnO films on Si substrates than on buffer layer/Si. The film grown on Si showed the highest quality of photoluminescence (PL) characteristics. The Al donor energy level depth $(E_d)$ of Al-N codoped ZnO films was reduced to about 50 meV, and the N acceptor energy level depth $(E_a)$ was reduced to 63 meV.

이온 이온주입한 p-type 4H-SiC에의 오믹 접촉 형성 (Formation of Ohmic Contacts on acceptor ion implanted 4H-SiC)

  • 방욱;송근호;김형우;서길수;김상철;김남균
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.290-293
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    • 2003
  • Ohmic contact characteristics of Al ion implanted n-type SiC wafer were investigated. Al ions implanted with high dose to obtain the final concentration of $5{\times}10^{19}/cm^3$, then annealed at high temperature. Firstly, B ion ion implanted p-well region were formed which is needed for fabrication of SiC devices such as DIMOSFET and un diode. Secondly, Al implanted high dose region for ohmic contact were formed. After ion implantation, the samples were annealed at high temperature up to $1600^{\circ}C\;and\;1700^{\circ}C$ for 30 min in order to activate the implanted ions electrically. Both the inear TLM and circular TLM method were used for characterization. Ni/Ti metal layer was used for contact metal which is widely used in fabrication of ohmic contacts for n-type SiC. The metal layer was deposited by using RF sputtering and rapid thermal annealed at $950^{\circ}C$ for 90sec. Good ohmic contact characteristics could be obtained regardless of measuring methods. The measured specific contact resistivity for the samples annealed at $1600^{\circ}C\;and\;1700^{\circ}C$ were $1.8{\times}10^{-3}{\Omega}cm^2$, $5.6{\times}10^{-5}{\Omega}cm^2$, respectively. Using the same metal and same process of the ohmic contacts in n-type SiC, it is found possible to make a good ohmic contacts to p-type SiC. It is very helpful for fabricating a integrated SiC devices. In addition, we obtained that the ratio of the electrically activated ions to the implanted Al ions were 10% and 60% for the samples annealed at $1600^{\circ}C\;and\;1700^{\circ}C$, respectively.

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