• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.7 no.2
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• pp.26-33
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• 2011

To evaluate steam oxidation behaviours of Alloy 617 and Haynes 230, oxidation test were performed at $900^{\circ}C$ in steam and $steam+20\;vol.-%\;H_2$ environments. Oxidation rate in steam condition was similar to that in air for Alloy 617, while it was slightly lower for Haynes 230. When hydrogen was added to steam, oxidation rate was enhanced. Isolated $MnTiO_3$ particle were formed on $Cr_2O_3$ oxide layer and sub layer $Cr_2O_3$ were formed in steam and $steam+20\;vol.-%\;H_2$ for Alloy 617. On the other hands, $MnCr_2O_3$ layer were formed on top of $Cr_2O_3$ oxide layer for Haynes 230. The extensive sub layer $Cr_2O_3$ formation was resulted from the oxygen inward diffusion in such environments. When hydrogen was added, the oxide morphology was changed from polygonal to platelet because of the accelerated diffusion of cations under the oxide layer. In addition, decarburized zone was extended as hydrogen participated into the reactions causing carbide dissolution.

• Carbon letters
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• v.14 no.4
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• pp.247-250
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• 2013

In this study, we present a facile method of fabricating graphene oxide (GO) films on the surface of polyimide (PI) via layer-by-layer (LBL) assembly of charged GO. The positively charged amino-phenyl functionalized GO (APGO) is alternatively complexed with the negatively charged GO through an electrostatic LBL assembly process. Furthermore, we investigated the water vapor transmission rate and oxygen transmission rate of the prepared (reduced GO $[rGO]/rAPGO)_{10}$ deposited PI film (rGO/rAPGO/PI) and pure PI film. The water vapor transmission rate of the GO and APGO-coated PI composite film was increased due to the intrinsically hydrophilic property of the charged composite films. However, the oxygen transmission rate was decreased from 220 to 78 $cm^3/m^2{\cdot}day{\cdot}atm$, due to the barrier effect of the graphene films on the PI surface. Since the proposed method allows for large-scale production of graphene films, it is considered to have potential for utilization in various applications.

• Journal of the Korean institute of surface engineering
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• v.41 no.1
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• pp.6-11
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• 2008

An Indium Zinc Oxide(IZO) transparent conductive layer was deposited on a large size glass substrate by using magnetron dc sputtering method with varying a deposition temperature. As the deposition temperature decreased to a room temperature, the sheet resistance of IZO film increased. But this deposition temperature range is included in an applicable to a device. From a standpoint of the sheet resistance, the differences of the sheet resistance were not great and the uniformity of the layer was uniformed around 10%. Crystallization particles were shown on the surface of the layer as deposition temperature increased, but these particles were not shown on the surface of the layer as deposition temperature decreased to the room temperature. It didn't make a scrap of difference in a transmittance of varying deposition temperature. Therefore, it is concluded that IZO thin film manufactured by the room temperature deposition condition can be used as a large size transparent conductive layer of a liquid crystal display device.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.319.1-319.1
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• 2013

Solid oxide fuel cells (SOFCs) have been recognized as one of emerging renewable energy sources, due to minimized pollutant production and high efficiency in operation. The performance of SOFCs is largely dependent on the electrode polarization which involves the oxidation/reduction in cathodes and anodes along with the charge transport of ions and electronic carriers. Atomic layer deposition is based on the alternate chemical surface reaction occurring at low temperatures with high uniformity and superior step coverage. Such features can be extended into the coating of metal oxide and/or metal layer onto the porous materials. In particular, the atomic layer deposition is can manipulated in controlling the charge transport in terms of triple phase boundaries, in order to control artificially the electrochemical polarization in electrodes of SOFC. The current work applied atomic layer deposition of metal oxides intro the electrodes of SOFCs. The corresponding effect was monitored in terms of the electrochemical characterization. The roles of atomic layer deposition in solid oxide fuel cells are discussed towards optimized towards long-term durability at intermediate temperature.

• Journal of the Korean institute of surface engineering
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• v.20 no.2
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• pp.49-59
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• 1987

The properties of $Cr_2O_3-Al_2O_3-SiO_2$ composite oxide coatings on steel surface were investigated. The results obtained were as follows: The microhardness of oxide coating layer increased with increasing heat-treatment temperature and $Cr_2O_3$ content in coating layer. The hardness showed the highest value (850Hv) treated at 700$^{\circ}C$ for $SiO_2:Al_2O_3:Cr_2O_3$=1:1:4. Increasing heat-treatment temperature, corrosion current density became lower and coating layer became denser. The corrosion current density showed the lowest value $(6.5{\times}10^{-5}\;Acm^2)$ treated at 750$^{\circ}C\;for\;SiO_2:Al_2O_3:Cr_2O_3$=1:1:3. These results were explained by protective layer which was formed during heat-treatment. The bonding between matrix and coating layer is expected to be made mechanically and chemically by the inter diffusion of Ni and Fe. The composite oxide coating was formed by softening of the binder with increasing heat-treatment temperature. The strengthening of coating layer is to be resulted from the dispersion of major oxide particles.

• Electrical & Electronic Materials
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• v.9 no.8
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• pp.789-798
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• 1996

The double nitride layer Metal Nitride Oxide Semiconductor(MNOS) structures were fabricated by variating both gas ratio and nitride thickness, and by duplicating nitride deposited and one nitride layer MNOS structure to improve nonvolatile memory characteristics of MNOS structures by Low Pressure Chemical Vapor Deposition(LPCVD) method. The nonvolatile memory characteristics of write-in, erase, memory retention and degradation of Bias Temperature Stress(BTS) were investigated by the homemade automatic .DELTA. $V_{FB}$ measuring system. In the trap density double nitride layer structures were higher by 0.85*10$^{16}$ $m^{-2}$ than one nitride layer structure, and the AVFB with oxide field was linearly increased. However, one nitride layer structure was linearly increased and saturated above 9.07*10$^{8}$ V/m in oxide field. In the erase behavior, the hole injection from silicon instead of the trapped electron emission was observed, and also it was highly dependent upon the pulse amplitude and the pulse width. In the memory retentivity, double nitrite layer structures were superior to one nitride layer structure, and the decay rate of the trapped electron with increasing temperature was low. At increasing the number on BTS, the variance of AVFB of the double nitride layer structures was smaller than that of one nitride layer structure, and the trapped electron retention rate was high. In this paper, the double nitride layer structures were turned out to be useful in improving the nonvolatile memory characteristics.

• Journal of the Korean Electrochemical Society
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• v.6 no.2
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• pp.158-160
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• 2003

We have reported to make nanostructured cobalt oxide electrode that have large capacitance over than 400 F/g (specific capacitance) and good cycleability. But, it had serious demerits of low voltage range under 0.5 V and low power density. Therefore, we need to increase voltage range of cobalt oxide electrode. We report here on the electrochemical properties of sol-gel-derived nanoparticulate cobalt xerogel in 1M KOH solution and aqueous polymeric gel electrolyte. In solution electrolyte, cobalt oxide electrode had over 250 F/g capacitance consisted of EDLC and pseudocapacitance. In gel electrolyte, cobalt oxide electrode had around 100 F/g capacitance. This capacitance was only electric double layer capacitance of active surface area. In solution electrolyte, potassium ion as working ion reacted with both of layers easily. However, In gel electrolyte, reacted with only surface-active layer. Itis very hard to reach resistive layer. So, we have studied on pretreatment of electrode to contain working ions easily. We'll report more details.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.200-202
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• 2009

Tin oxide thin films were prepared by atomic layer deposition using a tetrakis(ethylmethylamino) tin precursor without any seed layer. The average growth rate of tin oxide film is about 1.2 A/cycle from $50{^{\circ}C}$ to $150{^{\circ}C}$. The rate decreases rapidly at a substrate temperature of $200{^{\circ}C}$. ALD-grown tin oxide thin film was characterized with the use of XRD, AFM and XPS. Due to a thermal annealing effect, the surface roughness and the tin amount in the film composition are slightly increased.