• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.178-178
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• 2010

With the scaling down of ULSI(Ultra Large Scale Integration) circuit of CMOS(Complementary Metal Oxide Semiconductor)based electronic devices, the electronic devices become more faster and smaller size that are promising field of semiconductor market. However, very narrow line width has some disadvantages. For example, because of narrow line width, deposition of conformal and thin barrier is difficult. Besides, proportion of barrier width is large, thus resistance is high. Conventional PVD(Physical Vapor Deposition) thin films are not able to gain a good quality and conformal layer. Hence, in order to get over these side effects, deposition of thin layer used of ALD(Atomic Layer Deposition) is important factor. Furthermore, it is essential that copper atomic diffusion into dielectric layer such as silicon oxide and hafnium oxide. If copper line is not surrounded by diffusion barrier, it cause the leakage current and devices degradation. There are some possible methods for improving the these secondary effects. In this study, TaNx, is used of Tertiarybutylimido tris (ethylamethlamino) tantalum (TBITEMAT), was deposited on the 24nm sized trench silicon oxide/silicon bi-layer substrate with good step coverage and high quality film using plasma enhanced atomic layer deposition (PEALD). And then copper was deposited on TaNx barrier using same deposition method. The thickness of TaNx was 4~5 nm. TaNx film was deposited the condition of under $300^{\circ}C$ and copper deposition temperature was under $120^{\circ}C$, and feeding time of TaNx and copper were 5 seconds and 5 seconds, relatively. Purge time of TaNx and copper films were 10 seconds and 6 seconds, relatively. XRD, TEM, AFM, I-V measurement(for testing leakage current and stability) were used to analyze this work. With this work, thin barrier layer(4~5nm) with deposited PEALD has good step coverage and good thermal stability. So the barrier properties of PEALD TaNx film are desirable for copper interconnection.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.17-20
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• 2001

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35{\mu}m$ Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by $0.35{\mu}m$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and $Si_{2}NO$ species near the new $Si-SiO_{2}$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the $Si-SiO_{2}$ interface and contributed to electron trap generation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.87-87
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• 2011

Oxide semiconductors are attractive materials for thin-film electronics and optoelectronics due to compatibility with synthesis on large-area, glass and flexible substrate. However, development of thin-film electronics has been hampered by the limited number of semiconducting oxides that are p-type. We report on the effect of the oxygen partial pressure ratio in the gas mixture on the electrical and optical properties of spinel Mg:$ZnCo_2O_4$ thin films deposited at room temperature using RF sputtering, that exhibit p-type conduction. The thin-films are deposited at room temperature in a background of oxygen using a polycrystalline Mg:$ZnCo_2O_4$ ablation target. The p-type conduction is confirmed by positive Seebeck coefficient and positive Hall coefficient. The electrical resistivity and carrier concentration in on dependent Mg:$ZnCo_2O_4$ thin films were found to be dependent on the oxygen partial pressure ratio. As a result, it is revealed that the Mg:$ZnCo_2O_4$ thin-films were greatly influenced on the electrical and optical properties by the oxygen partial pressure condition. The visible region of the spectrum of 36~85%, and hole mobility of 1.1~3.7 $cm^2$/Vs, were obtained.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.199-199
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• 2011

Recently, Thin film transistors (TFTs) with amorphous oxide semiconductors (AOSs) can offer an important aspect for next generation displays with high mobility. Several oxide semiconductor such as ZnO, $SnO_2$ and InGaZnO have been extensively researched. Especially, as a well-known binary metal oxide, tin oxide ($SnO_2$), usually acts as n-type semiconductor with a wide band gap of 3.6eV. Over the past several decades intensive research activities have been conducted on $SnO_2$ in the bulk, thin film and nanostructure forms due to its interesting electrical properties making it a promising material for applications in solar cells, flat panel displays, and light emitting devices. But, its application to the active channel of TFTs have been limited due to the difficulties in controlling the electron density and n-type of operation with depletion mode. In this study, we fabricated staggered bottom-gate structure $SnO_2$-TFTs and patterned channel layer used a shadow mask. Then we compare to the performance intrinsic $SnO_2$-TFTs and doping hafnium $SnO_2$-TFTs. As a result, we suggest that can be control the defect formation of $SnO_2$-TFTs by doping hafnium. The hafnium element into the $SnO_2$ thin-films maybe acts to control the carrier concentration by suppressing carrier generation via oxygen vacancy formation. Furthermore, it can be also control the mobility. And bias stability of $SnO_2$-TFTs is improvement using doping hafnium. Enhancement of device stability was attributed to the reduced defect in channel layer or interface. In order to verify this effect, we employed to measure activation energy that can be explained by the thermal activation process of the subthreshold drain current.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• 한국전기전자재료학회논문지
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• 제33권4호
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• pp.281-285
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• 2020

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

• 전기전자학회논문지
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• 제27권4호
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• pp.567-572
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• 2023

본 논문에서는 Partial isolation lateral double diffused metal oxide semiconductor(Pi-LDMOS)의 항복전압에 대해 시뮬레이션을 통해 분석하였다. 항복전압 변화는 Partial buried oxide(P-BOX)의 다양한 파라미터(길이, 두께, 위치)에 따라 조사되었고, 그 메커니즘에 대해 명기하였다. 또한 항복전압과 trade-off 관계에 있는 온저항의 변화를 P-BOX 파라미터 변화에 따라 분석하였고 Figure of merit(FOM)을 계산하여 비교하였다. 제안된 구조에서 L_box=5㎛, t_box=2㎛, L_bc=2㎛일 경우 138V의 가장 높은 항복전압을 나타내었고, L_box=5㎛, t_box=1.6㎛, L_bc=2㎛일 경우 가장 높은 FOM을 나타내었다. 이는 conventional LDMOS 대비 항복전압은 123%, FOM은 3.89배 향상된 수치이다. 따라서 Pi-LDMOS는 높은 항복전압과 FOM을 가져 Power IC의 안정적인 동작범위 향상에 기여할 수 있다.

• 한국결정성장학회지
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• 제8권3호
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• pp.424-430
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• 1998

MONOS(metal-oxide-nitride-oxide-semicondutor) EEPROM에 응용하기 위한 얇은 ONO 유전층의 막 특성을 AES, SIMS, TEM 및 AFM을 이용하여 조사하였다. 터널링 산화막, 질화막, 블로킹 산화막의 두께를 각각 달리하여 ONO 박막을 제작하였다. 터널링 산화막 위에 LPCVD방법으로 질화막을 증착하는 동안 얇은 터널링 산화막이 질화되었으며, 질화막 위에 블로킹 산화막을 형성할 때, 산소가 질화막 표면을 산화시킬 뿐만 아니라 질화막을 지나 확산되었다. ONO 박막은 $SiO_2$(블로킹 산화막)/O-rich SiOxNy(계면)/N-rich iOxNy(질화막)/O-rich SiOxNy(터널링 산화막)으로 이루어졌다. SiON상은 주로 터널링 산화막과 질화막, 질화막과 블로킹 산화막 계면에 분포하였으며, $Si_2NO$상은 각 계면의 질화막 쪽과 터널링 산화막 내에 분포하였다.

• 한국재료학회지
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• 제26권6호
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• pp.342-346
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• 2016

To observe the bonding structure and electrical characteristics of a GZO oxide semiconductor, GZO was deposited on ITO glasses and annealed at various temperatures. GZO was found to change from crystal to amorphous with increasing of the annealing temperatures; GZO annealed at $200^{\circ}C$ came to have an amorphous structure that depended on the decrement of the oxygen vacancies; increase the mobility due to the induction of diffusion currents occurred because of an increment of the depletion layer. The increasing of the annealing temperature caused a reduction of the carrier concentration and an increase of the bonding energy and the depletion layer; therefore, the large potential barrier increased the diffusion current dna the Hall mobility. However, annealing temperatures over $200^{\circ}C$ promoted crystallinity by the defects without oxygen vacancies, and then degraded the depletion layer, which became an Ohmic contact without a potential barrier. So the current increased because of the absence of a potential barrier.