An Analysis Technique for Interconnect Circuits with Multiple Driving Gates in Deep Submicron CMOS ASICs (Deep Submicron CMOS ASIC에서 다중 구동 게이트를 갖는 배선회로 해석 기법)
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- Journal of the Korean Institute of Telematics and Electronics C
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- v.36C no.12
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- pp.59-68
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- 1999