• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.526-528
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• 2008

LLC series resonant converter has many unique characteristics and improvement over PWM topologies. However, many output capacitors should be needed in parallel to satisfy an output voltage ripple and a rated ripple current of the capacitors. This paper is deal with a novel two phase interleaved LLC resonant converter using a phase of the resonant capacitor. The proposed converter can satisfy output voltage ripple and a rated ripple current of capacitors with few output capacitors, relatively. The operation and features is considered in detail and a prototype with a 12V-100A output is investigated.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2243-2257
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• 2016

This paper presents a two stage three-phase proton exchange membrane fuel cell (PEMFC) generation system. When the system is connected to a three-phase load, it is very sensitive to the characteristics and type of the load. Especially unbalanced three-phase loads, which result in a pulsating power that is twice the output frequency at the inverter output, and cause the dc-link to generate low frequency ripples. This penetrates to the fuel cell side through the front-end dc-dc converter, which makes the fuel cell work in an unsafe condition and degrades its lifespan. In this paper, the generation and propagation mechanism of low frequency ripple is analyzed and its impact on fuel cells is presented based on the PEMFC output characteristics model. Then a novel method to evaluate low frequency current ripple control capability is investigated. Moreover, a control scheme with bandpass filter inserted into the current feed-forward path, and ripple duty ratio compensation based on current mode control with notch filter is also proposed to achieve low frequency ripple suppression and dynamic characteristics improvement during load transients. Finally, different control methods are verified and compared by simulation and experimental results.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1429-1435
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• 2012

DC-DC converter commonly used in photovoltaic systems, fuel cell systems and electric vehicles is a boost converter. The interleaved boost converter, connected in parallel by several boost converters and operated by the phase difference to reduce the input and output current ripple, has been widely used in recent years. Because of small input and output current ripples, the circuit can reduce the size of the input and output capacitors. Thus, instead of conventional electrolytic capacitor, the film capacitor with high reliability can be used and this is the life and reliability of the entire system can be improved. In this paper, the output current ripple formulas of the multi-stage interleaved boost converter are derived, and the characteristics in accordance with duty are found out. In order to verify the abovementioned contents, the derived results will make a comparison with the calculated values by using PSIM tool.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.355-356
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• 2015

This paper proposes a control strategy of total output power ripple cancellation for both of Machine-Side Converter (MSC) and Grid-Side Converter (GSC) in a DFIG under unbalanced grid conditions. The proposed control strategy for the MSC is the zero torque ripple control algorithm with an enhanced LVRT capability. The control algorithm for the MSC exhibits reduced torque pulsation in steady-state unbalanced grid conditions. In addition, this control algorithm also minimizes a peak value of rotor current in transient unbalanced grid conditions. The total output power ripple cancellation control algorithm is adopted in the GSC. The total output power ripple cancellation is achieved by nullifying the oscillating component of the total output active and reactive power at the summing point of stator and rotor of DFIG. The proposed control strategy for the GSC reduces the output power oscillation leading to the improved quality of wind farms output.

• Journal of Power Electronics
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• v.12 no.2
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• pp.249-257
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• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2204-2206
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• 1997

A novel zero voltage and zero current switching (ZVZCS) full bridge (FB) PWM converter with a low output current ripple is proposed. The proposed circuit improve the demerits of the previously presented ZVBCS-FB-PWM converters[5-8] such as use of lossy components or additional active switches. A simple auxiliary circuit which includes neither lossy components nor active switches provides ZVZCS conditions to primary switches, ZVS for leading-leg switches and ZCS for lagging-leg switches. In addition, this proposed circuit reduces a output current ripple considerably. Many advantages including simple circuit topology, high efficiency, low cost and low current ripple make the new converter attractive far high power (> 1kW) applications.

• Journal of Power Electronics
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• v.14 no.5
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• pp.908-917
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• 2014

For the purpose of designing an intrinsic safety Flyback converter with minimal output voltage ripple based on a specified output current, this paper first classified the energy transmission modes of the system into three sorts, namely, the Complete Inductor Supply Mode-CCM (CISM-CCM), the Incomplete Inductor Supply Mode-CCM (IISM-CCM) and the Incomplete Inductor Supply Mode-DCM (IISM-DCM). Then, the critical secondary self-inductance assorting the three modes are deduced and expressions of the output voltage ripples (OVR) are presented. For a Flyback converter with constant loads and switching frequency, it is shown that the output voltage ripple in the CISM-CCM is the smallest and that it has no relationship with the secondary self-inductance. Otherwise, the OVR of the other two modes are bigger than the previously mentioned one. It is concluded that the critical inductance between the CISM-CCM and the IISM-CCM is the minimal secondary self-inductance to ensure the smallest output voltage ripple. At last, a design method to guarantee the minimum OVR within the scales of the input voltage and load are analyzed, and the minimum secondary self-inductance is proposed to minimize the OVR. Simulations and experiments are given to verify the results.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1429-1437
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• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
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• v.5 no.2
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• pp.151-159
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• 2005

The errors generated from current measurement paths are inevitable, and they can be divided into two categories: offset error and scaling error. The current data including these errors cause periodic speed ripples which are one and two times the stator electrical frequency respectively. Since these undesirable ripples bring about harmful influences to motor driving systems, a compensation algorithm must be introduced to the control algorithm of the motor drive. In this paper, a new compensation algorithm is proposed. The signal of the integrator output of the d-axis current regulator is chosen and processed to compensate for the current measurement errors. Usually the d-axis current command is zero or constant to acquire the maximum torque or unity power factor in the ac drive system, and the output of the d-axis current regulator is nearly zero or constant as well. If the stator currents include the offset and scaling errors, the respective motor speed produces a ripple related to one and two times the stator electrical frequency, and the signal of the integrator output of the d-axis current regulator also produces the ripple as the motor speed does. The compensation of the current measurement errors is easily implemented to smooth the signal of the integrator output of the d-axis current regulator by subtracting the DC offset value or rescaling the gain of the hall sensor. Therefore, the proposed algorithm has several features: the robustness in the variation of the mechanical parameters, the application of the steady and transient state, the ease of implementation, and less computation time. The MATLAB simulation and experimental results are shown in order to verify the validity of the proposed current compensating algorithm.

• Journal of Power Electronics
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• v.10 no.3
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• pp.328-333
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• 2010

A photovoltaic power conditioning system (PV PCS) that contains single-phase dc/ac inverters tends to draw an ac ripple current at twice the output frequency. Such a ripple current perturbs the operating points of solar cells continuously and it may reduce the efficiency of the current based maximum power point tracking technique (CMPPT). In this paper, the ripple current generation in a dc link and boost inductor is analyzed using the ac equivalent circuit of a dc/dc boost converter. A new feed-forward ripple current compensation method to incorporate a current control loop into a dc/dc converter for ripple reduction is proposed. The proposed feed-forward compensation method is verified by simulation and experimental results. These results show a 41.8 % reduction in the peak-to peak ac ripple. In addition, the dc/ac inverter control system uses an automatic voltage regulation (AVR) function to mitigate the ac ripple voltage effect in the dc link. A 3kW PV PCS prototype has been built and its experimental results are given to verify the effectiveness of the proposed method.