• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1154-1157
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• 2006

Organic thin-film transistors (OTFTs) based on a semiconducting polymer have been fabricated using an organic patterning methodology. Laser assisted lift-off (LALO) technique, ablating selectively the hydrophobic layer by an excimer laser, was used for producing a semiconducting polymer channel in the OTFT with high resolution. The selective wettability of a semiconducting polymer, poly (9-9-dioctylfluorene-co-bithiophene) (F8T2), dissolved in a polar solvent was found to define precisely the pattering resolution of the active channel. It is demonstrated that in the F8T2 TFTs fabricated using the LALO technique and is applicable for the larger area display.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.147-148
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• 2005

We report on high-performance organic field-effect transistors by promoting surface-mediated two-dimensional molecular ordering in organic semiconductor. To achieve this goal, we have controlled the intermolecular interaction at the interface between organic semiconductor and the insulator substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.465-465
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• 2013

Inorganic 물질인 SiO2 dielectric 위에 organic dielectric PVP (4-vinyphenol)를 spin coating으로 올려, inorganic/organic dielectric 형태의 double layer구조로 High-performance amorphous indiumgallium zinc oxide thin-film transistors (IGZO TFT)를 제작하여 보았다. SiO2 dielectric을 buffer layer로 80 nm, PVP는 10Wt% 400 nm로 구성하였으며, 200 nm single SiO2 dielectric과 동일한 수준의 leakage current 특성을 MIM Capacitor 구조를 통해서 확인할 수 있었다. 이 소자의 장점은 용액공정의 도입으로 공정 시간의 단축 및 원가 절감을 이룰 수 있으며, dielectric과 channel 사이의 균일한 interface의 형성으로 interface trap 개선 및 Yield 향상의 장점을 갖는다. 우리는 실험을 통해서 SiO2 buffer layer가 수직 electric field에 의한 leakage current을 제어하고, PVP dielectric은 interface를 개선하는 것을 확인하였다. Vth의 negative shift 및 slope의 향상으로 구동전압이 줄어들고, 균일한 I-V Curve 형성을 통해서 Process Yield의 향상을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1319-1321
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• 2009

Copper phthalocyanine (CuPc) Field-effect transistors (FETs) was successfully fabricated on plastic substrates. Orientation of CuPc crystallites on substrate could be obtained via rubbing process. It was revealed that CuPc crystallites were perpendicularly aligned on PES substrates with the rubbing direction. The performance of FETs was affected by orientation of CuPc on rubbed substrates.

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.99-102
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• 2004

In this work the electrical characteristics of organic thin film transistors with the surface-treated organic gate insulator have been studied. For the surface treatment of gate dielectric, Ar plasma was used. Pentacene and PVP were used as active and dielectric layers respectively. Pentacene was thermally evaporated in vacuum at a pressure of about $10^{-6}$ Torr and at a deposition rate of 0.5 $\AA$/sec. PVP was spin coated and cured at $100^{\circ}C$. before pentacene deposition. organic thin film transistors with surface-treated gate insulators have provided improved operation characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.198-198
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 1997.02a
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• pp.67-67
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• 1997

• Bulletin of the Korean Chemical Society
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• v.33 no.7
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• pp.2127-2128
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• 2012

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.69-70
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• 2000

There are currently considerable interest in the applications of conjugated polymers, oligomers, and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field-effect transistors and light-emitting diodes. In this study, pentacene thin-film transistors (TFTs) were fabricated on glass substrate. Aluminums were used for gate electrodes. Silicon dioxide was deposited as a gate insulator by PECVD and patterned by reactive ion etching (R.I.E). Gold was used for the electrodes of source and drain. The active semiconductor pentacene layer was thermally evaporated in vacuum at a pressure of about $10^{-8}$ Torr and a deposition rate $0.3{\AA}/s$. The fabricated devices exhibited the field-effect mobility as large as 0.07 $cm^2/V.s$ and on/off current ratio as larger than $10^7$.

• Journal of Electrical Engineering and Technology
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• v.4 no.1
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• pp.118-122
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• 2009

Organic thin film transistors with a pentacene active layer and various polymer gate insulators were fabricated and their performances were investigated. Characteristics of pentacene thin film transistors on different polymer substrates were investigated using an atomic force microscope (AFM) and x-ray diffraction (XRD). The pentacene thin films were deposited by thermal evaporation on the gate insulators of various polymers. Hexamethyldisilazane (HMDS), polyvinyl acetate (PVA) and polymethyl methacrylate (PMMA) were fabricated as the gate insulator where a pentacene layer was deposited at 40, 55, 70, 85, 100 oC. Pentacene thin films on PMMA showed the largest grain size and least trap concentration. In addition, pentacene TFTs of top-contact geometry are compared with PMMA and $SiO_2$ as gate insulators, respectively. We also fabricated pentacene TFT with Poly (3, 4-ethylenedioxythiophene)-Polysturene Sulfonate (PEDOT:PSS) electrode by inkjet printing method. The physical and electrical characteristics of each gate insulator were tested and analyzed by AFM and I-V measurement. It was found that the performance of TFT was mainly determined by morphology of pentacene rather than the physical or chemical structure of the polymer gate insulator