• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.4
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• pp.313-319
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• 2019

Induction motors connected with a three-phase AC system may malfunction due to reverse phase or open phase faults. Conventional overcurrent relays and overheating relays are used to prevent such accidents; however, their drawbacks include a low response speed and false operation. Therefore, in this study, a digital relay for the reverse-open phase was designed and fabricated. This relay can detect the reverse phase and open phase faults and send a trigger signal to the control circuit. The proposed relay was developed based on a microcontroller. The detection times of the reverse phase and open phase were verified as 320ms and 80ms, respectively. Compared with conventional relays that only protect the motor from one type of fault, the proposed relay can detect both, reverse phase and open phase faults. In addition, the fault detection, identification criterion, and trigger signal patterns can be modified by programming according to the requirements of users.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1185-1187
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• 1987

Digital systems are increasingly being used in the ranges of many control engineering. The residue number system offers the possibility of high speed operation and error correction. The compact self-checking pulse-train residue arithmetic circuit is proposed. A fault tolerant digital filter is practically implemented using these proposed circuits.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.628-638
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• 1997

This paper describes an implementation of fault simulator that can switch level fault models such as transistor stuck-open and stuck-closed faults as well as stuck-at faults. It overcomes the limitation when only stuck-at faults are used in VLSI circuits. Signal flow of a transistor switch is bidirectional in its nature, but most of signal flows in a switch level circuits, about 95%, are in one direction. This fault simulator focuses on the way which changes a switch level circuit into a graph model with two directed edges. Two paths from Vdd to ground and from ground to directions. Logic simulation is performed along dominant signal flows. The switch level fault simulation estimates the dominant path by injecting switch-level fualts, and pattern vectors are used for faults simulation. Experimental results are shown to demonstrate correctness of the fault simulator.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.42-48
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• 1990

In this paper robust test generation for stuck-open faults in CMOS circuits is proposed. By obtaining initialization patterns and test patterns using the relationship of bit position and Hamming weight among input vectors for CMOS circuit test generation time for stuck-open faults can be reduced, and the problem of input transition skew which make fault detection difficult is solved, and the number of test sequences are minimized. Also the number of test sequences is reduced by arranging test sequences using Hamming distance between initialization patterns and test patterns for circuit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1538-1543
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• 2009

The electric ballast for ceramic metal halide lamp needs a protection circuit to prevent from over voltage and over current in the case that the lamp or the electric ballast are in faults. In this paper, cost-effective and high performance protection circuit is proposed for the electric ballast. The proposed protection circuit is adapted to the electric ballast with $LC_SC_P$ resonance type half bridge inverter. The experimental results demonstrate that the proposed circuit can protect effectively under open and short fault conditions.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.185-187
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• 2000

Fault current is flowed into 154/23kV M. Tr when line-to-ground fault occurs in power system. NGR(Neutral Grounded Reactor) is set up in order to prevent M.Tr fault by limiting magnitude of fault currents. Here, disconnection of NGR causes voltage increase by L-C resonance and line-to-ground fault in an unearthed system results in voltage increase at healthy phases. So Over Voltage Ground Relay(OVGR) is used for tripping M.Tr. Also, buses at second phases of M.Trs are all connected with section circuit breakers closed for the purpose of parallel operation and load shedding. In case of speciality buses are comprised of power cable in part for GIS connection. When no-load charged cable or bus is open by a section CB, unbalanced voltage charged on the bus is induced. Also discrepant opening time for circuit breakers on different phases gives rise to unbalanced zero sequence voltage. It was observed that this zero sequence voltage detected in the 22.9kV P.T (Potential Transformer for bus) mal-operated 59GT and tripped M.Tr. The zero sequence voltage of which vanishing time is longer than relay operating time came out by EMTDC simulation. Also, it was shown that the voltage waves of actual test are similar to those of simulation. On the basis of above results, R-C circuit complement on the relay without any effect on a power system made operating time of the relay longer than vanishing time of distorted waves. Consequently, operating time of the relay was delayed and magnitude of distorted waves was decreased by increasing time constant of the relay.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.1
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• pp.112-116
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• 2010

As one of the countermeasures to improve the recovery characteristics of the SFCL (superconducting fault current limiter), the method using the trigger of high-TC superconducting element (HTSC) when the quench in the HTSC element occurred was proposed. To confirm the suggested method, the control circuit to detect the quench occurrence of HTSC element in case of the fault occurrence was designed and the current limiting and recovery experiments of the SFCL using the designed control circuit were performed. Through the analysis for the experimental results, the points of both the open time and the closing time of a power switch comprising the control circuit could be adjusted by the resistance amplitude of a normal conducting current limiting resistor (CLR) and the recovery characteristics of the SFCL together with the current limiting operation could be confirmed to be improved by using the control circuit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.9
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• pp.1583-1589
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• 2016

This paper proposes an improved spread spectrum time domain reflectometry (ISSTDR) using time-frequency correlation and reference signal elimination method in order to have more accurate fault determination and location detection than conventional (SSTDR) despite increased signal attenuation due to the long distance to cable fault location. The proposed method has a two-step process: the first step is to detect a peak location of the reference signal using time-frequency correlation analysis, and the second step is to detect a peak location of the correlation coefficient of the reflected signal by removing the reference signal. The proposed method was validated through comparison with existing SSTDR methods in open-and short-circuit fault detection experiments of low voltage power cables. The experimental results showed that the proposed method can detect correlation coefficients at fault locations accurately despite reflected signal attenuation so that cable faults can be detected more accurately and clearly in comparison to existing methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.1
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• pp.33-39
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• 2022

A multi-phase brushless direct current (BLDC) motor is widely used in large-capacity electric propulsion systems such as submarines and electric ships. In particular, in the field of military submarines, the polyphaser motor must suppress torque ripple in various failure situations to reduce noise and ensure stable operation for a long time. In this paper, we propose a polyphaser current control method that can improve efficiency and reduce torque ripple by minimizing the increase in stator winding loss at maximum output torque by controlling the phase angle and amplitude of the steady-state current during open circuit failure of the stator winding. The proposed control method controls the magnitude and phase angle of the healthy phase current, excluding the faulty phase, to compensate for the torque ripple that occurs in the case of a phase open failure of the motor. The magnitude and phase angle of the controlled steady-state current are calculated for each phase so that copper loss increase is minimized. The proposed control method was verified using hardware-in-the-loop simulation (HILS) of a 12-phase BLDC motor. HILS verification confirmed that the increase in the loss of the stator winding and the magnitude of the torque ripple decreased compared with the open phase fault of the motor.