• Journal of Communications and Networks
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• v.13 no.1
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• pp.70-76
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• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• Current Research on Agriculture and Life Sciences
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• v.8
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• pp.107-113
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• 1990

This study was attempted to develop a remote controllable speed sprayer in order to protect an operator from agricultural chemicals. For the purpose of remote controllable transmission was developed by using one chip microcomputer. The following results could be summarized in this study. 1. Remote controllable transmission developed had not made even a single mistake during the test performed 100 times repeat. Thus, it could that this machine was very accurate. 2. One chip microcomputer was made by machine language and its was with in 3 sec's which was the same as human did. 3. One chip microcomputer which was used in the experiment could be widely used to automation of agricultural machinery, since it is smaller and chiper than any other similar ones such as personal computer, lap tap, one board computer. 4. Since, farm tractor has the same type of transmission as this system, it also could be adapted to farm tractors. 5. In this experiment, transmission lever was remote controll were designed to operate simultaneously. Thus, this system developed was more complicate than conventional system. However, by removing this transmission lever and by mounting the remote controll system at the speed sprayer, it would be higher and easier to handle than the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.151-155
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• 2002

This paper presents a micro fluxgate magnetic sensor in printed circuit board (PCB). The fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a micro patterned amorphous magnetic ribbon with extremely high DC permeability of ∼100,000 and the core has a rectangular-ring shape. The amorphous magnetic core is easily saturated due to the low coercive field and closed magnetic path for the excitation field. Four outer layers as an excitation and pick-up coils have a planar solenoid structure. The chip size of the fabricated sensing element is 7.3${\times}$5.7m㎡. Excellent linear response over the range of -100${\mu}$T to +100${\mu}$T is obtained with 540V/T sensitivity at excitation square wave of 3V$\_$P-P/ and 360kHz. The very low power consumption of ∼8mW was measured. This magnetic sensing element which measures the lower fields than 50${\mu}$T, is very useful for various applications such as: portable navigation systems, military research, medical research, and space research.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.8
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• pp.702-707
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• 2002

This paper presents a micro fluxgate sensor in printed circuit board (PCB). The fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a micro patterned amorphous magnetic ribbon and the core has a rectangular-ring shape. The amorphous magnetic core is easily saturated due to the low coercive field and closed magnetic path for the excitation field. Four outer layers as an excitation and pick-up coils have a planar solenoid structure. The chip size of the fabricated sensing element is 7.3$\times$5.7$\textrm{mm}^2$. Excellent linear response over the range of -100$\mu$T to +100$\mu$T is obtained with 540V/T sensitivity at excitation square wave of 3 $V_{p-p}$ and 360kHz. The very low power consumption of ~8mW was measured. This magnetic sensing element, which measures the lower fields than 50$\mu$T, is very useful for various applications such as: portable navigation systems, military research, medical research, and space research.h.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.83-90
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• 2004

This paper describes on-board decentralized data acquisition system that acquires and encodes the numerous sensor data distributed on the big flight vehicles efficiently. The system's sub-units which have one encoder unit and several remote units were designed and simulated according to the communication protocols and the control, sequence logics based on the FPGA chip. And we have made the functional verification of the acquisition, collection and formatting of remote analog and digital data for the manufactured hardwares.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.54-58
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• 2012

In this paper, we implemented total monitoring system in which LED light turned on only when user detected and LED light turned out only when user disappeared. This system is composed of two modules, one is HW board based on Micro Controller and the other is SW control system based on Web server. Micro controller board is based on ATMega2560 chip which is connected with Infra Red and Ultra sonic sensors. Web based monitoring system was designed can be used in smart device. The validity of this monitoring system was proved by integration test of two modules.