• Journal of the Korean Society of Marine Environment & Safety
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• v.21 no.1
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• pp.97-102
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• 2015

The long line fishing machine is combined with motor and two disc rollers has used on the small size fishing-boat under 1 ton located in near Jeollanam-do seaside. The long line fishing motor is controlled only one direction because the fishing line is loaded heavily at pulling up. On this paper we made the long line fishing 400W power motor controller which it was usually applied under 1 ton fishing boat, and designed the controller using PWM chip, Half bridge driver and MOSFET for one direction motor control. Furthermore some user convenience devices were added like battery indicator and safety protection circuit for battery overdischarge and battery source wire mismatch connection. So we protected the battery from overdicharging when the battery voltage was below 11.5V and fishermen didn't need to worry about source lines misconnection anymore. We confirmed the test version of controller was the good working condition at land and sea.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Proceedings of the Korean Society for Bioinformatics Conference
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• 2003.10a
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• pp.66-72
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• 2003

Toxicogenomics is now emerging as one of the most important genomics application because the toxicity test based on gene expression profiles is expected more precise and efficient than current histopathological approach in pre-clinical phase. One of the challenging points in Toxicogenomics is the construction of intelligent database management system which can deal with very heterogeneous and complex data from many different experimental and information sources. Here we present a new Toxicogenomics database developed as a part of 'Toxicogenomics for Efficient Safety Test (TEST) project'. The TEST database is especially focused on the connectivity of heterogeneous data and intelligent query system which enables users to get inspiration from the complex data sets. The database deals with four kinds of information; compound information, histopathological information, gene expression information, and annotation information. Currently, TEST database has Toxicogenomics information fer 12 molecules with 4 efficacy classes; anti cancer, antibiotic, hypotension, and gastric ulcer. Users can easily access all kinds of detailed information about there compounds and simultaneously, users can also check the confidence of retrieved information by browsing the quality of experimental data and toxicity grade of gene generated from our toxicology annotation system. Intelligent query system is designed for multiple comparisons of experimental data because the comparison of experimental data according to histopathological toxicity, compounds, efficacy, and individual variation is crucial to find common genetic characteristics .Our presented system can be a good information source for the study of toxicology mechanism in the genome-wide level and also can be utilized fur the design of toxicity test chip.

• IMMUNE NETWORK
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• v.5 no.4
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• pp.205-214
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• 2005

Background: We examined global gene expression profiles of peripheral blood mononuclear cells (PBMCs) in patients with ulcerative colitis (DC), and tested whether the identified genes with the altered expression might be associated with susceptibility to UC. Methods: PBMCs from 8 UC and 8 normal healthy (NH) volunteers were collected, and total RNAs were subjected to the human 8.0K cDNA chip for the micro array analysis. Real time-PCR (RT-PCR) was performed to verify the results of micro array. One hundred forty UC patients and 300 NH controls were recruited for single nucleotide polymorphism (SNP) analysis. Results: Twenty-five immune function-related genes with over 2-fold expression were identified. Of these genes, two chemokines, namely, CXCL1 and CCL20, were selected because of their potential importance in the evocation of host innate and adaptive immunity. Four SNPs were identified in the promoter and coding regions of CXCL1, while there was no significant difference between all patients with UC and controls in their polymorphisms, except minor association at g.57A>G (rs2071425, p=0.02). On the other hand, among three novel and one known SNPs identified in the promoter region of CCL20, g. -1,706 G>A (p=0.000000055), g. -1,458 G>A (p=0.0048), and g. -962C>A (p=0.0006) were found to be significantly associated with the susceptibility of Uc. Conclusion: Altered gene expression in mononuclear cells may contribute to IBD pathogenesis. Although the findings need to be confirmed in other populations with larger numbers of patients, the current results demonstrated that polymorphisms in the promoter region of CCL20 are positively associated with the development of Uc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.34-44
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• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.31-37
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• 2001

Digital servo implementation in optical servo chip has been spotlighted since it is easy to integrate with other blocks and it has less sensitive characteristics change in terms of temperature variation and better flexibility to the system variation like pick-up. Therefore, Optical disc players adopted digital servo are increasing in market. However, one drawback of digital signal processor embedded digital servo is power consumption that is one of the most important factors of portable optical disc player system. For that reason, this paper introduces new architecture to reduce power consumption of digital servo by means of reducing DSP load but increasing minimum hardware size. The main idea of reducing power consumption of digital servo greatly is utilizing CDP characteristics as most operations are done and used up most operating steps of DSP at the initial time, but most power consumption is occurred in play mode. Therefore, if operating steps for digital filtering in play mode could be reduced greatly, power consumption of overall system can be reduced greatly. This paper shows an example that low power digital servo architecture whose current is reduced almost 83%, compare to that of digital servo which is not applied by the low power architecture introduced in this paper.

• Journal of Mechanical Science and Technology
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• v.18 no.5
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• pp.770-779
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• 2004

This paper describes the micro cutting of wear resistant tungsten carbides using PCD (Poly-Crystalline Diamond) cutting tools in performance with SEM (Scanning Electron Microscope) direct observation method. Turning experiments were also carried out on this alloy (V50) using a PCD cutting tool. One of the purposes of this study is to describe clearly the cutting mechanism of tungsten carbides and the behavior of WC particles in the deformation zone in orthogonal micro cutting. Other purposes are to achieve a systematic understanding of machining characteristics and the effects of machining parameters on cutting force, machined surface and tool wear rates by the outer turning of this alloy carried out using the PCD cutting tool during these various cutting conditions. A summary of the results are as follows: (1) From the SEM direct observation in cutting the tungsten carbide, WC particles are broken and come into contact with the tool edge directly. This causes tool wear in which portions scrape the tool in a strong manner. (2) There are two chip formation types. One is where the shear angle is comparatively small and the crack of the shear plane becomes wide. The other is a type where the shear angle is above 45 degrees and the crack of the shear plane does not widen. These differences are caused by the stress condition which gives rise to the friction at the shear plane. (3) The thrust cutting forces tend to increase more rapidly than the principal forces, as the depth of cut and the cutting speed are increased preferably in the orthogonal micro cutting. (4) The tool wear on the flank face was larger than that on the rake face in the orthogonal micro cutting. (5) Three components of cutting force in the conventional turning experiments were different in balance from ordinary cutting such as the cutting of steel or cast iron. Those expressed a large value of thrust force, principal force, and feed force. (6) From the viewpoint of high efficient cutting found within this research, a proper cutting speed was 15 m/min and a proper feed rate was 0.1 mm/rev. In this case, it was found that the tool life of a PCD tool was limited to a distance of approximately 230 m. (7) When the depth of cut was 0.1 mm, there was no influence of the feed rate on the feed force. The feed force tended to decrease, as the cutting distance was long, because the tool was worn and the tool edge retreated. (8) The main tool wear of a PCD tool in this research was due to the flank wear within the maximum value of $V_{max}$ being about 260 $\mu\textrm{m}$.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.249-256
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• 2007

AIn this paper, a new desist of LDI controller IC for general purpose is proposed for driving the LDI(LCD Driver Interface) controller in $4{\sim}9$ inches sized portable small-medium TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display) panel module. The designed LDI controller was verified on the FPGA(Reld Programmable Gate Array) test board, and was made the interactive operation with the commercial TFT-LCD panel successfully. The purpose of design is that it is standardized the LDI controller's operation by one LDI controller for driving all TFT-LCD panel without classifying the panel vendor, and size. The main advantage for new general-purpose LDI controller is the usage for the desist of all panel's SoG(System on a Glass) module because of the design for the standard operation. And in the previous method, it used each LDI controller for every LCD vendor, and panel size, but because a new one can drive all portable small-medium sized panel, it results in reduction of LDI controller supply price, and manufacturing cost of AV(Audio Video) board and panel. In the near future, the development of SoG IC(Integrated Circuit) for manufacturing more excellent functional TFT-LCD panel module is necessary. As a result of this research, the TFT-LCD panel can make more small size, and light weight, and it results in an upturn of domestic company's share in the world market. With the suggested theory in this paper, it expects to be made use of a basic data for developing and manufacturing for the SoG chip of TFT-LCD panel module.

• Proceedings of the Korean Society of Crop Science Conference
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• 2022.10a
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• pp.269-269
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• 2022

Pre-harvest sprouting (PHS) on rice panicles is getting problematic in recent several years in Korea due to climate changes such as high temperature and more frequent typhoons during harvesting season. PHS negatively affects grain quality severely and also yield. Genetic improvement of Korean varieties (Oryza sativa ssp. japonica) through a marker assisted-backcross breeding (MAB) with the known PHS resistant genes must be one of ideal solutions. However, the final breeding products of MAB occasionally exhibit unwanted traits, especially the cross between genetically distant parents. This might be caused by linkage drag and/or presence of the gene-unlinked donor introgressions, resulting that the final products could not be released to the farmers. The major PHS resistance gene, Sdr4 (Seed dormancy 4) originated from an indica cultivar, Kasalath was selected as a donor gene. In order to avoid unexpected phenotypes in the breeding products, we performed a precision marker-based breeding (PMBB) consisting of foreground, recombinant, and background selections (FS, RS, and BS) which aim to develop 'single small introgression lines' (~100 kb introgression). Korean varieties (Ilpum and Gopum) were crossed with Kasalath. We developed Sdr4-allele specific markers for FS and a set of polymorphic flanking markers near the Sdr4 (-350kb and +420kb) for RS. To minimize linkage drag, the small introgression (< 125kb) containing Sdr4 was selected in Ilpum background (BC₂F₄) through 1^st RS with ~1,200 F₂ or BC₁F₂ plants (one side trimmed) and then 2^nd RS with ~1,000 progenies from the 1^st RS selected plants (another side trimmed). After RS, the selected lines were genotyped by using Infinium 7K SNP chip to detect other donor introgressions and the lines were backcrossed. Currently BS is on-going from the backcross-derived progenies with BS markers to remove residual introgressions. During the PMBB process, genetic effect of Sdr-4-Kasalath allele was confirmed in Ilpum and Gopum backgrounds by PHS phenotyping using the segregating BC₂F₃ or BC₁F₄ materials. The Sdr4 PMBB lines in Ilpum background (< 125kb introgression) will be valuable genetic resources to improve PHS resistance in modem popular temperate japonica varieties.