• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.925-928
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• 1999

A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

• Korean Journal of Computational Design and Engineering
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• v.18 no.1
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• pp.21-27
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• 2013

Presented in the paper is a log data based modeling method for effective construction of a virtual plant model which can be used for the virtual PLC (Programmable Logic Controller) simulation. For the PLC simulation, the corresponding virtual plant, consisting of virtual devices, is required to interact with the input and output symbols of a PLC. In other words, the behavior of a virtual device should be the same as that of the real device. Conventionally, the DEVS (Discrete Event Systems Specifications) formalism has been used to represent the behavior a virtual device. The modeling using DEVS formalism, however, requires in-depth knowledge in the simulation area, as well as the significant amount of time and efforts. One of the key ideas of the proposed method is to generate a plant model based on the log data obtained from the production system. The proposed method is very intuitive, and it can be used to generate the full behavior model of a virtual device. The proposed approach was applied to an AGV (Automated Guided Vehicle).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2697-2701
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• 2012

The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.347-353
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• 2012

In this paper, authors will develop the quick and precise remote controller of automatic fire detection equipment (P-type one-class receiver) based on information communication technology (IT). The remote controller detects the fire and disaster in the building automatically and quickly and then activates the facilities to extinguish the fire and disaster, monitoring such situation in a real time through wire-wireless communication network. The proposed remote controller is applied a programmable logic device (PLD) micom. of one-chip type which is small size and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLD micom. analyzes digital signals from sensors, then activates fire extinguishing facilities for alarm and rapid suppression in a case of fire and disaster. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication, and then the situation room sends an emergency alarm signal. The automatic fire detection equipment (AFDE) based on IT will minimize the life and wealth loss while prevents fire and disaster.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.67-79
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• 2009

Because a product in the car industry has a short life cycle in recent years, the process planning and the manufacturing lines have to be changed frequently. Most of time, repositioning an existing facility and modifying used control information are faster than making completely new process planning. However, control information and control code such as PLC code are difficult to understand. Hence, industries prefer writing a new control code instead of using the existing complex one. It shows the lack of information reusability in the existing process planning. As a result, to reduce this redundancy and lack of reusability, we propose a SOS-Net modeling method. SOS-Net is a standard methodology used to describe control information. It is based on the Device Structure which consists of sensor information derived from device hardware information. Thus, SOS-Net can describe a real control state for automated manufacturing systems. The SOS-Net model is easy to understand and can be converted into PLC Code easily. It also enables to modify control information, thus increases the reusability of the new process planning. Proposed model in this paper plays an intermediary role between the process planning and PLC code generation. It can reduce the process planning and implementation time as well as cost.

• ALGAE
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• v.25 no.1
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• pp.37-44
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• 2010

A tide-simulating apparatus was developed for culturing marine macroalgae. The objective of this study was to introduce a novel tide-simulating apparatus that can simulate a diurnal or semi-diurnal tidal cycle in the laboratory. In this apparatus, the seaweeds are move up and down and the water level remains the same during the simulated tidal cycle. The apparatus consists of 18 cylindrical culture tanks (3 blocks $\times$ 6 culture tanks) with 12 cm diameter and 24.5 cm long containing up to 2.5 L of seawater. There is a horizontal plate which covered all 18 culture tanks, and it is raised and lowered by a programmable motor that can regulate exposure time. In one application, seaweeds are attached to braided twine hung on Plexiglas air-tubing. The air-tubing is attached to a lid that is set on a horizontal plate. This apparatus is made of colorless Plexiglas to maximize light transmittance. This apparatus is easily disassembled and transportable to any indoor laboratory, wet laboratory, greenhouse, etc. This apparatus also offers considerable flexibility in terms of design. The size of culture tank can be redesigned by either increasing the height of cylinder or/and using a different diameter of cylindrical Plexiglas, therefore, larger/taller thalli can be cultivated. Growth rates of three eulittoral Porphyra species from different tidal elevations have been compared using this device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.306-316
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• 2016

In this paper, an NMOS-diode eFuse OTP (One-Time Programmable) memory cell is proposed using a parasitic junction diode formed between a PW (P-Well), a body of an isolated NMOS (N-channel MOSFET) transistor with the small channel width, and an n+ diffusion, a source node, in a DNW (Deep N-Well) instead of an NMOS transistor with the big channel width as a program select device. Blowing of the proposed cell is done through the parasitic junction formed in the NMOS transistor in the program mode. Sensing failures of '0' data are removed because of removed contact voltage drop of a diode since a NMOS transistor is used instead of the junction diode in the read mode. In addition, a problem of being blown for a non-blown eFuse from a read current through the corresponding eFuse OTP cell is solved by limiting the read current to less than $100{\mu}A$ since a voltage is transferred to BL by using an NMOS transistor with the small channel width in the read mode.