• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.510-512
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• 2009

A volumetric 3D display system based on a rotating two dimensional color LED array is set up. It has a cylinder display space ${\Phi}800{\times}640mm3$ which is composed of 256 slices of pictures in one 3D image with each slice $320{\times}256$ LED pixels. The volumetric image has 4 gray scales and 64 colors. The main structure and working principle of the system is described in detail.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1136-1141
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• 2004

In recent years, demands on microelectrode have been greatly enhanced because of its potential applications and mass production of microelectrodes is needed. An electrochemical fabrication is used as an method for the simple and cheap fabrication of multi microelectrodes. In this paper, one dimensional microelectrode array is used for fabricating of multi electrodes. A diffusion layer which is formed near the electrode surface has an effect on the shape error of multi microelectrodes. The optimal distance between electrodes to minimize shape errors of multi electrodes is investigated. Multi microelectrodes which has several tens of and hundreds of micrometer in diameter are fabricated at a time.

• The Journal of the Korea Contents Association
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• v.6 no.6
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• pp.50-55
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• 2006

This paper presents a scheme which scrambles and descrambles images from multiple video channels. A combined image frame is formed by concatenating the incoming frames from channels in a two dimensional array. This algorithm employs an encryption scheme on row and column numbers of the combined image frame and thereby yields an encrypted combined image. The proposed algorithm is to encrypt multiple images at a time since it recomposes images from multiple video channels yielding one by composite image, and encrypts the composite image resulting In higher security.

• Journal of KIISE:Databases
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• v.29 no.4
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• pp.247-261
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• 2002

Aggregation is an important operation that affects the performance of OLAP systems. In this paper we define a new class of aggregation queries, called range-groupby queries, and present a method for processing them. A range-groupby query is defined as a query that, for an arbitrarily specified region of an n-dimensional cube, computes aggregations for each combination of values of the grouping attributes. Range-groupby queries are used very frequently in analyzing information in MOLAP since they allow us to summarize various trends in an arbitrarily specified subregion of the domain space. In MOLAP applications, in order to improve the performance of query processing, a method of maintaining precomputed aggregation results, called the prefix-sum array, is widely used. For the case of range-groupby queries, however, maintaining precomputed aggregation results for each combination of the grouping attributes incurs enormous storage overhead. Here, we propose a fast algorithm that can compute range-groupby queries with minimal storage overhead. Our algorithm maintains only one prefix-sum away and still effectively processes range-groupby queries for all possible combinations of the grouping attributes. Compared with the method that maintains a prefix-sum array for each combination of the grouping attributes in an n-dimensional cube, our algorithm reduces the space overhead by (equation omitted), while accessing a similar number of cells.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.209-218
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• 2012

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

• Journal of Biomedical Engineering Research
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• v.25 no.6
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• pp.489-496
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• 2004

Insertion of cannulae into vessels may disturb the blood flow doing non-physiological load and stress on blood cells such that ADP may increase and result in hemolysis. Authors used the computational method to simulate the 3-dimensional blood flow inside of the cannula using numerical method. We limited the research to within the drainage cannulae with side holes inserted through the human vein. In this paper, 9 different cannulae with side holes categorized by the number of side holes of 4, 12, and 20, and also categorized by the array type of side holes of staggered array, in-line array, and alternative in-line array were studied and compared to the cannula with no side holes by using CFD analysis. We evaluated the flow rate, the wall shear stress, and the shear rate and compared them with one another to estimate the effect of the side holes. The flow rate is not proportional to the number of the side holes. However, larger number of side holes can reduce the mean shear rate. Both the number and the array type of side holes play an important role on the fluid dynamics of the blood flow in cannulae.

• The Journal of the Korea Contents Association
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• v.8 no.10
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• pp.37-44
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• 2008

This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.1
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• pp.68-74
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• 2000

Experimental investigation on flame spread along suspended droplet arrays have been conducted with various droplet spacings and ambient air velocities. Especially, an opposed air stream is introduced to simulate fundamental flame spread behaviors in spray combustion. High-speed chemiluminescence imaging technique of OH radicals has been adopted to measure flame spread rates and to observe various flame spread behaviors. The fuel used is n-Decane and the air velocity varies from 0 to 17cm/s. The pattern of flame spread is grouped into two: a continuous mode and an intermittent one. It is found that there exists droplet spcings, above which flame spread does not occur. The increase of ambient air velocity causes the limit droplet spacing of flame spread to become small due to the increase of apparent flame stretch. As the ambient air velocity decreases, flame spread rate increases and then decreases after taking a maximum flame spread rate. This suggests that there exists a moderate air flowing to give a maximum flame spread rate due to enhanced chemical reaction by the increase of oxidizer concentration.

• Journal of the Korean Society of Combustion
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• v.3 no.2
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• pp.1-11
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• 1998

Experimental investigation on flame spread of blended fuel droplet arrays has been conducted for droplet diameters of 1.0mm and 0.75mm using high-speed chemiluminescence images of OH radical. The flame spread rate is measured with blended fuel composition, droplet diameter, and droplet spacing. Flame spread is categorized into two: a continuous mode and an intermittent one. There exist a limit droplet spacing, above which flame does not spread, and a droplet spacing of maximum flame spread, which is closely related to flame diameter. It is seen that flame spread rate is mainly dependent upon the relative position of flame zone within a droplet spacing. In case of large droplet, the increase of % volume of Heptane induces the shift of limit droplet spacing to a larger spacing since volatile Heptane plays a role of an enhancer of flame spread rate. In case of small droplet, the increase of % volume of Heptane leads to the shift of limit droplet spacing to a smaller droplet spacing. This is so because of the delayed chemical reaction time by the rapid increase of mass flux of fuel vapor for small droplet.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.317-326
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• 2016

In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).