• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2000년도 하계종합학술대회논문집
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• pp.261-264
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• 2000

본 논문에서는 이동 통신용 단말기에 주로 사용되는 RF-chip inductor의 자동 외관검사를 위한 시스템 개발에 필요한 알고리즘을 제안하였다. 본 논문에서 제안한 방법은 영상취득 후 처리과정에서 동적 이진화 방법, 가산투영 등 영상처리에 관련된 방법을 이용해 코일 부분과 코어부분을 분리한 후 세선화 방법, 라벨링 방법 등을 적용하여 분리된 코일부분에 대해 코일의 감긴 회수와 피치간격의 불균일 검사를 수행하고 기준값 이상의 오차를 갖는 소자를 불량으로 처리하는 보다 개선된 처리방법을 제안하였으며 모의실험을 통해 성능을 검증하였다.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 1996년도 추계연구발표회 논문개요집
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• pp.68-69
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• 1996

• 전기학회논문지
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• 제58권2호
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• pp.363-368
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• 2009

In the paper, we confirmed improvement Noise figure of the entire RF front-end using spiral inductor with PGS(Patterned Ground Shield) and current bleeding techniques. LNA design is to achieve simultaneous noise and input matching. Spiral inductor in input circuit of LNA inserted PGS for betterment of Q-factor. we modeling inductor using EM simulator, so compared with inductor of TSMC 0.18um. We designed and simulation the optimum structure of PGS using Taguchi's method. We confirmed enhancement of noise figure at LNA after substituted for inductor with PGS. Mixer designed using current bleeding techniques for reduced noise. We designed LNA using inductor with PGS and Mixer using current bleeding techniques, so confirmed improvement of noise figure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.796-800
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• 2004

The main research on this paper is to model on-chip inductor in digital CMOS technology by using the foundry parameters and the physical structure. The s-parameters of a spiral inductor are extracted from the modeled equivalent circuit and then compared to the results obtained from HFSS. The structure and material of the inductor used for modeling in this work is identical with those of the inductor fabricated by CMOS process. To show why the modeled inductor instead of ideal inductor should be used to design a RF system, we designed dual band RF front-end receiver and then compared the results between when using the ideal inductor and using the modeled inductor.

• ETRI Journal
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• 제28권1호
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• pp.115-118
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• 2006

In this letter, a simple model parameter extraction methodology for an on-chip spiral inductor is proposed based on a wide-band inductor model that incorporates parallel inductance and resistance to model skin and proximity effects, and capacitance to model the decrease in series resistance above the frequency near the peak quality factor. The wide-band inductor model does not require any frequency dependent elements, and model parameters can be extracted directly from the measured data with some curve fitting. The validity of the proposed model and parameter extraction methodology are verified with various size inductors fabricated using $0.18\;{\mu}m$ CMOS technology.

• 융합신호처리학회논문지
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• 제1권1호
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• pp.89-96
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• 2000

본 논문에서는 이동 통신용 단말기에 주로 사용되는 RF-chip inductor의 자동 외관검사를 위한 시스템에 필요한 알고리즘을 제안하였다 제안한 방법은 취득한 영상에 국부적응 이진화 방법, 가산투영 기법을 적용하여 코일 부분과 코어 부분을 분리한다. 분리된 코일부분에 세선화(thinning) 방법, 체인코드(chain-code) 방법, 라벨링(labeling) 방법 등을 적용하여 코일성분을 추출하여 코일의 길이, 연결성, 코일의 turn수 그리고 피치간격에 의한 불균일 검사를 수행하여 소자의 불량 유무를 검사한다. 제안한 방법의 성능을 시험하기 위해 여러 가지 부품에 대한 모의실험을 통해 제안된 알고리즘의 성능을 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• 대한전자공학회논문지SD
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• 제45권5호
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• pp.58-64
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• 2008

CMOS $0.18{\mu}m$ 공정을 이용하여 1.8V supply voltage에서 6Gbps 이상의 처리속도를 가지는 1:2 demultiplexer(DEMUX)를 구현하였다. 높은 동작속도를 위하여 Current mode logic(CML)의 Flipflop을 사용하였으며 추가적인 동작속도 향상을 위하여 On-chip micro stacked spiral inductor($10{\times}10{\mu}m^2$)를 사용하였다. 총 12개의 인덕터를 사용하여 $1200{\mu}m^2$의 면적증가만으로 Inductive peaking의 효과를 나타낼 수 있었다. Chip의 측정은 wafer상태로 진행하였고 Micro stacked spiral inductor가 있는 1:2 demultiplexer와 그것이 없는 1:2 demultiplexer를 비교하여 측정하였다. 6Gbps에서 측정결과 Micro stacked spiral inductor를 1:2 demultiplexer가 inductor를 사용하지 않은 구조보다 Eye width가 약3%정도 증가하였고 또한 Jitter가 43%정도 감소하여 개선효과가 있음을 확인하였다. 소비전력은 76.8mW, 6Gbps에서의 Eye height는 180mV로 측정되었다.