• 한국정보과학회논문지:시스템및이론
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• 제36권2호
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• pp.102-110
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• 2009

컴퓨터 시스템 분야의 대표적인 문제 중 하나는 메모리의 처리 속도가 CPU의 처리 속도보다 매우 느리기 때문에 생기는 CPU 휴면 시간의 증가, 즉 메모리 장벽 문제이다. CPU와 메모리의 속도 차이를 줄이기 위해서는 레지스터, 캐시 메모리, 메인 메모리, 디스크로 대표되는 메모리 계층을 이용하여 자주 쓰이는 데이터를 메모리 계층 상위, 즉 CPU 가까이 위치시켜야 한다. 본 논문에서는 On-Chip SRAM을 이용한 임베디드 시스템 메모리 계층 최적화 기법을 리눅스 기반 시스템에서 최초로 제안한다. 본 기법은 시스템의 가상 메모리를 이용하여 프로그래머가 원하는 코드나 데이터를 On-Chip SRAM에 적재한다. 제안된 기법의 실험 결과 총 9개의 어플리케이션에 대하여 최대 35%, 평균 14%의 시스템 성능 향상과 최대 40% 평균 15%의 에너지 소비 감소를 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• ETRI Journal
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• 제40권6호
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• pp.759-773
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• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• 대한임베디드공학회논문지
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• 제6권6호
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• pp.345-359
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• 2011

In high performance embedded systems, the use of multiple on-chip memories is an essential architectural feature for exploiting inherent parallelism in multimedia applications. This feature allows multiple data accesses to be executed in parallel. However, it remains difficult to effectively exploit of multiple on-chip memories. The successful use of this architecture strongly depends on how to efficiently detect and exploit memory parallelism in target applications. In this paper, we propose a technique based on a linear array access descriptor [1], which is generated from profiled data, to detect and exploit memory parallelism. The proposed technique tackles an array reorganization problem to maximize memory parallelism in multimedia applications. We present preliminary experiments applying the proposed technique onto a representative coarse grained reconfigurable array processor (CGRA) with multimedia kernel codes. Our experimental results demonstrate that our technique optimizes data placement by putting independent data on separate storage. The results exhibit 9.8% higher performance on average compared to the existing method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.1109-1112
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• 1999

본 논문에서는 영상확대 chip의 video 입력부에 부분화면을 저장할 frame memory의 구조를 개선하고자 하였다. 영상확대 video scaler인 gm833×2는 입력단 측에 frame buffer memory가 필요하게 되지만, 이를 외부에 장착하려면 일반적으로 대용량의 FIFO 메모리를 사용하게 된다. 이것은 dualport SRAM으로 구성이 되며, 메모리 제어를 고가의 FIFO칩에 의존하는 결과를 가져온다. 또한 기존의 scaler chip은 단순히 확대처리만을 하며, 입력 전, 후에 data의 변경 또는 이미지처리가 불가능한 구조가 된다. 본 논문에서는 외부에 필요한 메모리를 내장한 새로운 기능의 chip을 설계하는 데에 있어 필수적인 메모리제어 로직을 제안하고자 한다. 여기서는 더 나은 기능의 향상된 메모리 제어회로를 제시하고 이를 One-chip에 집적할 수 있도록 하였다 이를 사용한 Video Scaler Processor chip은 SDRAM을 별도의 제어회로 없이 외부에 장착할 수 있도록 하여 scaler의 기능을 향상시키면서 전체 시스템의 구조를 간단히 할 수 있을 것으로 기대된다. 본 논문에서는 먼저 메모리 제어회로를 포함한 Video Scaler Processor chip의 메모리제어 하드웨어의 구조를 제시하고, 메모리 access model과 제어로직을 소개하고자 한다.

• 한국정보과학회논문지:시스템및이론
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• 제35권6호
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• pp.284-292
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• 2008

메모리 기술이 발달함에 따라 메모리의 집적도가 증가하게 되었고, 그에 따라 구성요소들의 크기가 작아지게 되고, 고장의 감응성이 증가하게 되어, 테스트는 더욱 복잡하게 된다. 또한, 칩 하나에 포함되어 있는 저장요소가 늘어남에 따라 테스트 시간도 증가하게 된다. SoC 기술의 발달로 대용량의 내장 메모리를 통합할 수 있게 되었지만, 테스트 과정은 복잡하게 되어 외부 테스트 환경에서는 내장 메모리를 테스트하기 어렵게 되었다. 본 논문은 ARM 프로세서 기반의 SoC 환경에서의 임베디드 메모리를 테스트할 수 있는 프로그램 가능한 메모리 내장 자체 테스트를 제안한다.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2011년 춘계학술대회논문집
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.