• 제목/요약/키워드: Offset Technique

검색결과 357건 처리시간 0.03초

새로운 디지털 인코딩 기법을 적용한 8비트 1GS/s 프랙셔널 폴딩-인터폴레이션 ADC (A 8b 1GS/s Fractional Folding-Interpolation ADC with a Novel Digital Encoding Technique)

  • 최동귀;김대윤;송민규
    • 전자공학회논문지
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    • 제50권1호
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    • pp.137-147
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    • 2013
  • 본 논문에서는 폴딩 구조에 저항열 인터폴레이션 기법을 적용한 1.2V 8b 1GS/s CMOS folding-interpolation A/D 변환기(ADC)에 대해 논한다. 기존 폴딩 ADC가 갖는 경계조건 비대칭 오차를 최소화하기 위해 홀수개의 폴딩 블록과 프랙셔널 폴딩 비율(fractional folding rate)을 사용하는 구조를 제안한다. 또한, 프랙셔널 폴딩기법을 구현하기 위해 덧셈기를 사용하는 새로운 디지털 인코딩기법도 제안한다. 그리고 iterating offset self-calibration 기법과 디지털 오차 보정 회로를 적용하여 소자 부정합과 외부 요인에 의한 노이즈 발생을 최소화하였다. 제안하는 A/D 변환기는 1.2V 0.13um 1-poly 6-metal CMOS 공정을 사용하여 설계 되었으며 $2.1mm^2$ 유효 칩 면적과(A/D 변환기 core : $1.4mm^2$, calibration engine : $0.7mm^2$), 350mW의 전력 소모를 나타내었다. 측정결과 변환속도 1GS/s에서 SNDR 46.22dB의 특성을 나타내었다. INL 과 DNL 은 자체보정회로를 통해 모두 1LSB 이내로 측정되었다.

Low-impedance Tetrodes using Carbon Nanotube-Polypyrrole Composite Deposition

  • Kim, Minseo;Shin, Jung Hwal;Lim, Geunbae
    • 센서학회지
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    • 제26권2호
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    • pp.73-78
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    • 2017
  • A tetrode is one of the neural electrodes, and it is widely used to record neural signals in the brain of a freely moving animal. The impedance of a neural electrode is an important parameter because it determines the signal-to-noise ratio of the recorded neural signals. Here, we developed a modification technique using carbon nanotube-polypyrrole composite nanostructures to decrease the impedances of tetrodes. The synthesis of the carbon nanotube and polypyrrole nanostructures was performed in two steps. In the first step, randomly dispersed carbon nanotubes and pyrrole monomers were gathered and aligned on the tetrode electrode. Next, they were electro-polymerized on the electrode surface. As the applied time (step-1 and step-2) and the offset voltage increased, the impedances of the tetrodes decreased. The modification technique is, therefore, an important and useful of lowering the impedances of tetrodes.

코팅원지 및 바인더가 코팅지의 인쇄적성에 미치는 영향 (Effect of Base Paper and Binder on the Printability of Coated Paper)

  • 이용규
    • 한국인쇄학회지
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    • 제15권2호
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    • pp.57-76
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    • 1997
  • A color halftoning is the process of generating halftone images for the different color plans, for example, cyan, magenta, yellow, and black for a offset printing device. A conventional halftone technique, so called AM screening, is simple and easy to implement, but the halftoned dot patterns by using this method is not free for the moire` fringe. Moire` patterns are caused the power spectrum distribution on low spatial frequency domain. To avoid Moire` patterns, the conventional screen require the different screen angles for each color plans. Recently, Ultra-fine and 7 color printing methods are developed to expend the color gamut. In 7 color printing method must be used the halftone technique of random and blue noise characteristic to avoid Moire` fringe.

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STBC 안테나 다이버시티를 이용한 MC-DS-CDMA 시스템의 성능 분석 (Performance Evaluation of MC-DS-CDMA Systems using STBC Antenna Diversity)

  • 최승국
    • 한국정보통신학회논문지
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    • 제13권2호
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    • pp.390-396
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    • 2009
  • MC-DS-CDMA 전송 방식에서는 서로 직교성이 있는 여러개의 부반송파들을 사용함으로서 주파수 다이버시티 효과를 얻을 수 있어 우수한 성능의 전송이 가능하다. 본 논문에서는 파일럿 심볼을 이용하여 채널을 추정하는 MC-DS-CDMA 시스템에 STBC 안테나 다이버시티 기법을 적용할 때의 시스템 성능을 분석한다. 이러한 다중 반송파 전송 방식에서는 채널 추정 에러, 비선형 전력 증폭기 및 송수신간 반송 주파수 편차 등에 의하여 시스템 성능이 열화 된다. 그러므로 위와 같은 영 향들을 모두 고려하여 송신 신호가 다중경로 페이딩 채널을 통하여 전송될 때의 데이터 비트 오류율 성능을 분석한다.

Finite element modeling of slab-on-beam concrete bridge superstructures

  • Patrick, Michael D.;Huo, X. Sharon
    • Computers and Concrete
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    • 제1권3호
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    • pp.355-369
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    • 2004
  • This paper presents a study of four finite element techniques that can be used to model slabon-beam highway bridges. The feasibility and correctness of each modeling technique are examined by applying them to a prestressed concrete I-beam bridge and a prestressed concrete box-beam bridge. Other issues related to bridge modeling such as torsional constant, support conditions, and quality control check are studied in detail and discussed in the paper. It is found that, under truck loading, the bending stress distribution in a beam section depends on the modeling technique being utilized. It is observed that the behavior of the bridge superstructure can be better represented when accounting for composite behavior between the supporting beams and slab.

Development of an Automatic Two-Dimensional Mesh Generator using an Inward Offset Boundary Technique

  • Choi, Jin-Woo;Kim, Yohng-Jo
    • 한국기계가공학회지
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    • 제2권4호
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    • pp.61-66
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    • 2003
  • An excellent mesh construction is of Importance in yielding good results of finite element analysis. The new mesh generation algorithm, which offsets boundaries inward, was developed on the basis of a looping method. An user interface technique and automatic splitting lines which both divide a given domain into subdomains manually or automatically, were used. In addition, the separation method has advantages to prevent the large scale of element size and to control numbers of nodes and elements. This new mesh generation algorithm was proved in practice.

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System Identification 기법을 이용한 이송중인 웹의 사행 거동에 대한 모델링 (Modeling of Lateral Dynamics of a Moving Web by Using the System Identification Technique)

  • 권순오;김상훈;신기현
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2002년도 추계학술대회 논문집
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    • pp.624-627
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    • 2002
  • Experimental study showed that the existing mathematical model doesn't fully describe the lateral motion of a moving web fur different operating conditions. So, a physically interpretable model of lateral motion of a moving web in a typical web guidance system, operated at Konkuk Univ., was developed using the system identification technique. A well-known Least Square Method based on ARX model was used for the system identification. Lateral displacement of the web was measured at the exit of each span by infrared sensors. The model obtained from identifying a linear time-invariant system for a typical operating condition yields an improved prediction capability of the lateral dynamics of the moving web compared to other mathematical models proposed in literature.

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3-D 지층의 굴절 및 반사 주시곡선 해석 연구 (A Study on Interpretation of Seismic Refraction and Reflection Traveltime Curves in 3-D Layers)

  • 양승진;유해수;박석재
    • 자원환경지질
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    • 제25권1호
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    • pp.79-85
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    • 1992
  • An Interpretation technique is presented to determine strike, dip, velocity and depth of 3-D planar layers from refraction or reflection traveltime curve. This interpretation technique determines the direction of emerging ray from the slope of the traveltime curve and traces the emerging ray to the refractor or reflector. The ray direction in the last layer is used to decide the normal vector to the refractor or reflector from whick its dip, strike and velocity are calculated. The vertical depth to the refractor or reflector is computed by using the intercept or zero-offset time and the ray direction in each layer. Some tests on the interpretation method are performed for the sysnthetic traveltimes generated in 3-D model layers and show that the paramerters of the model layers are accurately determined.

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유전자 알고리즘을 이용한 B-spline 곡면 피팅 (B-spline Surface Fitting using Genetic Algorithm)

  • ;김동준;민경철;표상우
    • 대한조선학회논문집
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    • 제46권1호
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    • pp.87-95
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    • 2009
  • The applicability of optimization techniques for hull surface fitting has been important in the ship design process. In this research, the Genetic Algorithm has been used as a searching technique for solving surface fitting problem and minimizing errors between B-spline surface and the ship's offset data. The encoded design variables are the location of the vertex points and parametric values. The sufficient accuracy in surface fitting implies not only various techniques for computer-aided design, but also the future production design.

저전력용 CMOS 비교기의 시스템 응용을 위한 옵셋 전압 최소화 기법 (An offset-voltage reduction technique for system applications of a low-power CMOS comparator)

  • 곽명보;이승훈;이인환
    • 전자공학회논문지C
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    • 제34C권12호
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    • pp.28-36
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    • 1997
  • In this paper, system application techniques of a low-voltage low-power CMOS comparator are proposed. The proposed techniques employ poly-layer lines instead of conventional dummy cells to improve the accuracy of comparators which are located in both ends of a comparator array. This technique is easily applicable for hihg-density systems such as memory. The proposed circuits are implemented using a 0.6 um signle-poly double-metal n-well CMOS technology and the dissipated power is 0.38 mW. at a 20MHz clock speed based on a 3V supply. The comparator offsets are measured separately and compared for system applications. Using the proposed techniues, the measured comparator offsets are reduced by 40% of a conventional case.

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