• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.405-408
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Aerospace Engineering and Technology
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• v.10 no.2
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• pp.114-120
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• 2011

Thermal control of satellite is mainly based on passive ways, such as the radiator made of aluminum honeycomb core with aluminum skins and OSR (Optical Solar Reflector). Additionally, for the thermal control of high dissipation unit, the aluminum doubler and heat pipe are utilized. Recently, efforts to find advanced thermal materials have been carried out to enhance heat rejection capability without increasing satellite size, weight and cost. This paper handles the carbon composites have high thermal conductivity with light weigh and have been considered as future thermal control materials to replace aluminum based radiator and doubler. Thermal analysis of satellite panel using APG(Annealed Pyrolytic Graphite) and carbon-carbon composites were performed and temperature contours were compared with the conventional thermal control methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1812-1819
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• 2001

In this paper, it investigated the permitted limit of the analog nonideality for the SOSOC Σ-Δ modulator design which is satisfied with 1 [MHz] signal bandwidth and 12-bit resolution in the OSR=25. Firstly, it get the SOSOC Σ-Δ modulator model and gain coefficient which is suitable in low voltage for the Σ-Δ modulator design which is satisfied with the specification in the supply voltage 3.3 [Vl. And it provided the performance prediction of the Σ-Δ modulator and the permitted limit of the nonideality by adding the performance degradation facts of the Σ-Δ modulator such as the finite gain of the amplifier, the SR, the closed-loop pole, the switch ON resistance and the capacitor mismatch to the ideal Σ-Δ modulator model. When designed the Σ-Δ modulator which is satisfied with the specification by the base above, it will be able to predict the performance of the Σ-Δ modulator and the guide for the specification of the circuit which composes the Σ-Δ modulator.

• Journal of Applied Biological Chemistry
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• v.57 no.2
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• pp.123-129
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• 2014

The antioxidant and antimicrobial activities of Camellia oleifera seed oil were studied. Four kinds of seed oil samples were prepared, crude oil and refined oil, extracted by cold pressing method (CPC, CPR), and organic solvent extraction (OSC, OSR). Antioxidant activity analysis was measured in 2,2-azinobis (3-ethylbenzothiazoline-6-sulfonic acid)-diammonium salt, ferric reducing Ability of Plasma, and 2,2-diphenyl-1-picrylhydrazyl assays. Besides, the percentage of inhibition of red blood cells hemolysis induced by 2,2'-azobis(2-amidnopropane) dihydrochlorid, the lag time of LDL conjugated dienes formation in vitro, and the inhibitors of loss in tryptophan fluorescence were all used to estimate the antioxidant activity of the samples. The total phenolic contents (TPC) were detemined by Folin-Ciocalteu method. The TPC of the C. oleifera seed oils can be arranged in descending order: CPC ($1.9172{\mu}g/mL$) > OSC ($1.5218{\mu}g/mL$) > CPR ($1.0611{\mu}g/mL$) > OSR ($0.6782{\mu}g/mL$). And the oils were investigated for activity against Escherichia coli, Bacillus subtilis, Saccharomyces cerevisiae and Aspergillus niger. The results showed the antioxidant activity of crude oil by cold pressing method was stronger than others, and all oils did inhibit activity of the top three bacteria expert A. niger. The further significance of the study contributes to measure the antioxidant and antimicrobial activity of the potential health benefits by the different methods of preparation and the oil of C. oleifera seeds acting as free radical scavenger, pharmaceuticals and preservatives may offer some information in medicine and cosmetic not just in food field.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2649-2655
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.75-78
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• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.437-438
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• 2008

This paper proposes a 8th-order single loop band-pass sigma-delta modulator that satisfies a wide bandwidth of 6MHz, which is required for a HDTV application. The proposed architecture is based on a simple analog structure that enlarges the noise shaping with a low OSR. In addition, a feedforward scheme is used to relax op-amp performance requirements. The proposed modulator has been simulated using the 0.18um 1.8v TSMC technology. The simulation results show that the bandwidth is 6MHz and SNQR is 70dB.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.348-352
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• 2017

In this paper, we propose a high resolution A/D converter for a sensor interface that processes low frequency AC signals. A 6b SAR ADC with low power consumption and a 11b incremental ADC with high resolution are combined together to perform 15b resolution. Conventional hybrid ADC has a disadvantage that it can convert t only DC signal, but in this paper, it is possible to convert data to AC signal by increasing input range of incremental ADC. The decimation filter is implemented on-chip. The designed Hybrid ADC operates at supply voltage of 1.8V and consumes the current of 6.98uA. The OSR (oversampling ratio) is 90. And SFDR, SNDR, ENOB and FoMs are 96.59dB, 88.47dB, 14.4-bit and 139.5dB, respectively.

• International Journal of Automotive Technology
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• v.6 no.5
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• pp.467-473
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• 2005

A continuously variable transmission (CVT) with an inner spherical traction drive was conceptually designed for bicycle usage. The range of the overall speed ratio is from 1.0 to 4.5. The rated power and pedal speed are 100 Watts and 6 rad/s, respectively. The peculiar packageability, high-level power efficiency and high torque capacity were considered in the design process. A compact CVT that can be installed within a $244\times125\times160mm^3$ space and is above 0.9 in efficiency for the rated values was numerically designed. The distribution of efficiency according to the input torque and input speed were calculated. Gradeability in the prescribed operation mode was simulated.