• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.305-309
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• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• Electrical & Electronic Materials
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• v.9 no.5
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.9-12
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• 1998

Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.17-22
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• 1999

In this paper, the results of the studies about a new proposal where the ONON(oxide-nitride-oxide-nitride) layer instead of the conventional ONO(oxide-nitride-oxide) layer is used as the IPD(inter-poly-dielectrics) layer to improve the data retention problem in the Flash EEPROM cell, have been discussed. For these studies, the stacked-gate Flash EEPROM cell with an about 10nm thick gate oxide and on ONO or ONON IPD layer have been fabricated. The measurement results have shown that the data retention characteristics of the devices with the ONO IPD layer are significantly degraded with an activation energy of 0.78 eV. which is much lower than the minimum value (1.0 eV) required for the Flash EEPROM cell. This is believed to be due to the partial or whole etching of the top oxide of the IPD layer during the cleaning process performed just prior to the dry oxidation process to grow the gate oxide of the peripheral MOSFET devices. Whereas the data retention characteristics of the devices with the ONON IPD layer have been found to be much (more than 50%) improved with an activation energy of 1.10 eV. This must be because the thin nitride layer on the top oxide layer in the ONON IPD layer protected the top oxide layer from being etched during the cleaning process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.5
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• pp.386-389
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• 2009

The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.451-456
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• 2021

In order to improve the cell capacitance and scale down in capacitors of semiconductor memory devices, a stacked ONO structure has been introduced as a dielectric layer and thinning of these layers has been attempted continuously. However, many problems have emerged in the manufacturing process. In this study, L/L LPCVD system was used to suppress the growth of natural oxide film of about 10 Å, which was able to secure the capacitance of 3fF / cell. In addition, we investigated the effect of thinning of the dielectric film on the abnormal oxidation of the nitride film, and proposed a stable process control method for forming the dielectric film to ensure oxidation resistance.