• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.643-644
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• 2006

In this paper, WiBro system which is one of the mobile wireless metropolitan area network systems is presented. WiBro is an OFDMA system which has a sub-channelization process unlike conventional OFDM systems. The sub-channelization is the time consuming processing, so a time-efficient hardware architecture is needed. WiBro RAS(Radio Access Station) demodulator is designed with Verilog HDL, and the gate count is 81k using the $0.18{\mu}m$ processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6A
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• pp.468-475
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• 2009

In OFDM-based Full Duplex Relays (FDR) with Decode and Forward (DF) scheme, an interference cancellation technique in the frequency domain is more efficient than the one in the time domain. However, an Inter-Symbol Interference (ISI) and Inter-Carrier Interference (ICI) may occur due to the timing mismatch between the feedback interference signal and the desired signal from Base Station (BS) when the feedback interference cancellation and demodulation are performed in the frequency domain. In this paper, the effects of timing mismatch on the synchronous type and asynchronous type of OFDM-based FDR are analyzed for uplink and downlink cases. Then, synchronization procedure and methods for reducing ISI and ICI in OFDM-based FDR with frequency-domain feedback interference canceller are proposed and verified by computer simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2731-2736
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• 2009

In this paper, a new implementation method of OFDM (orthogonal frequency division multiplexing) system with an orthogonal basis matrix is developed mathematically. The basis matrix is based on the Haar basis but has an appropriate form for modulation of multiple subchannel signals of OFDM. It is verified that the new basis matrix can be expanded with a simple recursive algorithm. The order of synthesis matrix in the transmitter is increased by the factor of two with every expansion. Demodulation in the receiver is carried out by its inverse matrix, which can be generated recursively with the orthogonal basis matrix. It is shown that perfect reconstruction of original signals is possibly achieved in the proposed OFDMsystem.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.659-662
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• 2005

A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.

• The Journal of the Acoustical Society of Korea
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• v.25 no.3
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• pp.113-120
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• 2006

This paper is concerned with a equalization technique for Orthogonal Frequency Division Multiplexing (OFDM) systems based on a block type pilot arrangement over slow fading channels. The bit rates obtained in underwater channels are relatively modest compared to some other communication channels such as cellular phones or indoor wireless systems. Consequently. the Doppler effect is the important parameter in tracking a channel. In case of a coherent demodulation scheme, the residual mean phase errors due to Doppler frequency may be fatal for the performance of the system. The equalizer could not solely handle mean Doppler shift. To account for the common Doppler effect a phase error tracking loop is used with the frequency equalizer. so that the rotation errors are avoided. Furthermore. simulations show that we can reduce the computational load of the tracking loop with negligible effect on performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.11
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• pp.1-8
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• 2011

In this paper, we study receiver design issue to apply the OFDM based WLAN specification, such as 802.11p, to the communications in high speed mobile environment, e.g., for the ICT based railroad control on a train having its speed up to 300 km/hr. To successfully apply the existing WLAN specifications without modifying its transmission format, the performance at the receiver will solely depends on the channel estimation performance if we ignore the affect of frequency offset With a speed of multiple hundred km/hr, the channel estimation using only the preamble will not provide enough precision since the channel changes so fast. Therefore, in this paper, taking the high mobility into account, we focus on the design of decision directed channel estimation and equalization techniques and perform simulations to evaluate and compare their performances and to finally confirm the applicability of the existing WLAN specification to the systems with very high mobility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.368-376
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• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• Journal of Broadcast Engineering
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• v.15 no.2
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• pp.224-231
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• 2010

In this paper, we analyze the performance of the cooperative relay communication system which uses orthogonal frequency division multiplexing(OFDM) with hierarchical subcarrier modulation. In the cooperative relay communication system, data transmission is accomplished in two time slots. In the first time slot, the source broadcasts the signal to the relay and to the destination. The relay demodulates the received signal, remodulates and forwards it to the destination in the second time slot. The source uses hierarchical modulation for subcarriers to deal with the signal-to-noise power ratio (SNR) difference in the source-relay and source-destination links. The bit error rate (BER) of the relay transmission system with hierarchical modulation depends on the hierarchical modulation parameter. First, we derive the relationship between BER and the parameter, and find the optimal parameter giving the minimum BER through computer simulations. Then, we analyze the performance of the proposed cooperative relay communication system according to the relay location. From this results, we find optimal relay location to maximize the BER performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.3
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• pp.229-235
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• 2019

The implementation of an in-band full-duplex wireless communication system is demonstrated in this study. In the analog/RF domain, the self-interference(SI) signal is reduced using a separate antenna for the transmitter and receiver paths, and most of the SI signal is canceled in the digital domain. A software defined radio(SDR) is used to implement the in-band full-duplex wireless communication system. The USRP X310 device uses transmitting and receiving antennas. By adjusting the gain of the transmitting and receiving ends of the SDR device, the magnitude of the SI signal entering the receiving antenna, and the size of the received signal from the outside, are both set to -64 dB. To verify the in-band full-duplex wireless communication performance, the source data is image and orthogonal frequency-division multiplexing is used for modulation. A WiFi standard frame with a carrier frequency of 2.67 GHz and bandwidth of 20 MHz is used. In the received signal, the SI signal is canceled by digital signal processing and the SI signal is attenuated by up to 34 dB. OFDM demodulation was impossible when the SI signal was not removed. However, the bit error rate is reduced to $2.63{\times}10^{-5}$ when the SI signal is attenuated by 34 dB, and no error is detected in the 100 Mbit data output as a result of passing through the Viterbi decoder.