• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.587-592
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• 2002

A new digital correlator fur an airborne synthetic aperture radiometer was designed in order to replace the conventional analog correlator unit which will become very complicated while the number of channels is increasing. The digital correlator uses digital IQ demodulator instead of the intermediate frequency (IF) phase shifter to make the correlation processing performed digitally at base band instead of analogly at IF. This technique has been applied to the digital receiver in softradio. The down-converted IF signals from each pair of receiver channels become low rate base-band digital signals after under-sampled, Digitally Down-Converted (DDC), decimated and filtered by FIR filters. The digital signals are further processed by two digital multipliers (complex correlation), the products are integrated by the integrators and finally the outputs from the integrators compose of the real part and the imaginary part of a sample of the visibility function. This design is tested by comparing the results from digital correlators and that from analog correlators. They are agreed with each other very well. Due to the fact that the digital correlators are realized with the help of Analog-Digital Converter (ADC) chips and the FPGA technology, the realized volume, mass, power consumption and complexity turned out to be greatly reduced compared with that of the analog correlators. Simulations show that the resolution of ADC has an influence on the synthesized antenna patterns, but this can be neglected if more than 2bit is used.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.12
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• pp.983-994
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• 1989

This paper presents a new variable structure model following control algorithm for control of manipulators. The reference model is a simple double integrators and the acceleration input for the robot manipulator consists of a proportional and derivative controller for the purpose of trajectory tracking. The control algorithm is derived by using Lyapunov stability theory instead of S.S < O, as is usual in the current VSS controller design. This proposed control algorithm does not require good knowledge of the parameter in the inertia matrix and is easily extendable to robot manipulators with a higher number of links. Also, the new algorithm is computationally fast because of not requiring the matrix inversion. The computer simulation was carried out to evaluate the performance of the proposed VSMFC.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.10a
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• pp.231-234
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• 2009

IEC 61850 based substation automation system is operating under digital network with a number of IEDs and a HMI as relation of server and client. In case of IEDs, before implementing the system, all of the system integrators require IEC 61850 certificate from individual IED manufacture. Otherwise, there is nothing to verify IED for constructing substation automation system at the real substation. This paper shows verification strategy of IEC 61850 communication reliability such as association /release, report, dataset and four type control function.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.87-89
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• 2005

The necessary and sufficient conditions for the linearization of the nonlinear control systems via restricted dynamic feed back have been found. These require checking with almost all indices from 0 to 2n-3. In this paper, we exploit the inherent structure of the system and find an efficient method to find linearizability of the system by reducing the range of the index to check. Our examples show the efficiency of our method.

• Korean Journal of Poultry Science
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• v.20 no.2
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• pp.107-114
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• 1993

The structure change in the broiler industry of Korea has been taking place very rapidly toward the direction of integrated production and marketing system. During the course of the evolution into the integrated structure, however, a number of small business entities, uncountable nationally but a minimum of a dozen, that previously engaged in the supply of production factors or live bird transaction also tended to get involved in the new system as a disguised or pseudo-integrator, having brought a lot of problems not only to the farmers but also to the development of integrated structure. The pseudo-integrator is generally characterized by limited functions in such a way of supplying chicks and feeds to and collecting grown birds from farmers under the contract at a fixed farmer's payment in practically the same pattern as a partial or quasi-integration, which intends to act as if an integrator in a stratagem to simply enjoy a margin simply from selling supplies and buying products for a certain period of time. The grower making a contract with appears to be a farmer who used to be an Independent and speculating but not able to join in the normal system of evolving integration. The problems of a pseudo-integrator center on the financial loss to a contract farmer, because the falsified integrator has to become easily bankrupt and run away when the price of live broiler continually stays below the cost of production, even though he is able to make a tremendous profit otherwise which is the real purpose of the operation for. It is true that the volatile market, fluctuating the price up more than doubled in a month and down to a half in a few weeks, makes the pseudo-integrator find the room for such a fraudulence. In addition, its activity also adversely affect the evolution of the integration due to rather negative image on structure change in general. It is recommended that the farmers need to better understand the real picture of the integrated system so as not to be swindled by a disguised, small scale agribusiness agent. By the same token, it is also equally required to have the whole industry integrated completely as early as possible. The Joint effort to get rid of pseudo-integrators' problems shall be put for the industry development moving toward the integration. No doubt a pseudo-integrator must be a temporary player for chance emerging during the course of structure change into the integrated, though.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.57-63
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• 2014

This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.