• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.203-204
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• 2005

PRAM (Phase change Random Access Memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change material has been researched in the field of optical data storage media. Among the phase change materials $Ge_2Sb_2Te_5$(GST) is very well known for its high optical contrast in the state of amorphous and crystalline. However, the characteristics required in solid state memory are quite different from optical ones. In this study, the structural properties of GST thin films with composition were investigated for PRAM. The 100-nm thick GeTe and $Sb_2Te_3$ films were deposited on $SiO_2$/Si substrates by RF sputtering system. In order to characterize the crystal structure and morphology of these films, we performed x-ray diffraction (XRD) and atomic force microscopy (AFM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.1
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• pp.91-95
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. But NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, log-structured filesystem was proposed such as YAFFS. However, YAFFS sequentially retrieves an array of all block information to allocate free block for a write operation. Also before the write operation, YAFPS read the array of block information to find invalid block for erase. These could reduce the performance of the filesystem. This paper suggests fast operation method for NAND flash filesystem that solves the above-mentioned problems. We implemented the proposed methods in YAFFS. And we measured the performance compared with the original technique.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.451-462
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• 2009

Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.390-390
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• 2012

Information technology industries has grown rapidly and demanded alternative memories for the next generation. The most popular random access memory, dynamic random-access memory (DRAM), has many advantages as a memory, but it could not meet the demands from the current of developed industries. One of highlighted alternative memories is magnetic random-access memory (MRAM). It has many advantages like low power consumption, huge storage, high operating speed, and non-volatile properties. MRAM consists of magnetic-tunnel-junction (MTJ) stack which is a key part of it and has various magnetic thin films like CoFeB, FePt, IrMn, and so on. Each magnetic thin film is difficult to be etched without any damages and react with chemical species in plasma. For improving the etching process, a high density plasma etching process was employed. Moreover, the previous etching gases were highly corrosive and dangerous. Therefore, the safety etching gases are needed to be developed. In this research, the etch characteristics of CoFeB magnetic thin films were studied by using an inductively coupled plasma reactive ion etching in $CH_4/O_2/Ar$ gas mixes. TiN thin films were used as a hardmask on CoFeB thin films. The concentrations of $O_2$ in $CH_4/O_2/Ar$ gas mix were varied, and then, the rf coil power, gas pressure, and dc-bias voltage. The etch rates and the selectivity were obtained by a surface profiler and the etch profiles were observed by a field emission scanning electron microscopy. X-ray photoelectron spectroscopy was employed to reveal the etch mechanism.

• Journal of the Korean Magnetics Society
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• v.19 no.1
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• pp.35-42
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• 2009

Among the next generation memory, MRAM (Magnetic Random Access Memory) is worthy of notice for substituting the preexisting memory thanks to its non-volatile property and other advantages. Recently perpendicular MRAM and spin transfer torque MRAM techniques are under active investigation to realize a high density and low power consumption. As a result, there are increasing of patents applications for high density, low current density for magnetization switching and high thermal stability. In this paper, we analyze the trend of patent applications and registrations about MRAM and propose a direction of future investigation.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.32-43
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• 2023

Resistive Random Access Memory (RRAM), based on resistive switching characteristics, is emerging as a next-generation memory device capable of efficiently processing large amounts of data through its fast operation speed, simple device structure, and high-density implementation. Interface type resistive switching offer the advantage of low operation currents without the need for a forming process. Especially, for RRAM devices based on transition metal oxides, various studies are underway to enhance the memory characteristics, including precise material composition control and improving the reliability and stability of the device. In this paper, we introduce various methods, such as doping of heterogeneous elements, formation of multilayer films, chemical composition adjustment, and surface treatment to prevent degradation of interface type resistive switching properties and enhance the device characteristics. Through these approaches, we propose the feasibility of implementing high-efficient next-generation non-volatile memory devices based on improved resistive switching properties.

• Journal of KIISE
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• v.42 no.4
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• pp.434-441
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• 2015

Next generation memory technologies, which we denote as 'new memory', have both non-volatile and byte addressable properties. These characteristics are expected to bring changes to the conventional computer system structure. In this paper, we propose a fast boot technique for hybrid main memory architectures that have both new memory and DRAM. The key technique used for fast booting is write-tracking. Write-tracking is used to detect and manage modified data detection and involves setting the kernel region to read-only. This setting is used to trigger intentional faults upon modification requests. As the fault handler can detect the faulting address, write-tracking makes use of the address to manage the modified data. In particular, in our case, we make use of the MMU (Memory Management Unit) translation table. When a write occurs to the boot completed state, write-tracking preserves the original state of the modified address of the kernel region to a particular location, and execution continues. Upon booting, the fast booting process restores the preserved data to the original kernel region allowing rapid system boot-up. We develop the fast booting technique in an actual embedded board equipped with new memory. The boot time is reduced to less than half a second compared to around 15 seconds that is required for the original system.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.23-31
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• 2011

Recently, Solid state disk is mainly used because this device has lower power consumption as well as higher response time. But it features higher price and lower performance at delete and write operations compared with HDD. To compensate this defect, Hybrid hard disk with internal non-volatile flash memory was issued. This NVCache is used as a kind of cache for disk blocks. In this paper, an I/O scheme for H-HDD is proposed for improving low power consumption as well as response time. Our method is to use this NVCache as read cache mainly and write cache when write requests are concentrated. In read cache operation, disk blocks with higher priority determined on basis of time as well as spatial localities are prefetched, which can improve response time. The write operation is conducted only at write peak time as disk spindle up costs higher battery power as well as response time. Experiments results show that the suggested method can improve response time of H-HDD and lower the power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.132-138
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• 2003

We investigated the polarization retention characteristics of ferroelectric capacitors with $Pb(Zr,Ti)O_3$ (PZT) thin films which were fabricated by different deposition methods. In thermally-accelerated retention tests, PZT films which were prepared by a chemical solution deposition (CSD) method showed rapid decay of retained polarization charges as the thickness of the films decreased down to 100 nm, while the films which were grown by metal organic chemical vapor deposition (MOCVD) retained relatively large non-volatile charges at the corresponding thickness. We concluded that in the CSD-grown films, the thicker interfacial passive layer compared with the MOCVD-grown films had an unfavorable effect on retention behavior. We observed the existence of such interfacial layers by extrapolation of the total capacitance with thickness of the films and the capacitance of these layers was larger in MOCVD-grown films than in CSD-grown films. Due to incomplete compensation of surface polarization charges by the free charges in the metal electrodes, the interfacial field activated the space charges inside the interfacial layers and deposited them at the boundary between the ferroelectric layer and the interfacial layer. Such space charges built up an internal field inside the films, which interfered with domain wall motion, so that retention property at last became degraded. We observed less imprint which was a result of less internal field in MOCVD-grown films while large imprint was observed in CSD-grown films.