• Title/Summary/Keyword: Node Speed

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Sensor Device Plug & Play for Ubiquitous Computing (유비쿼터스 컴퓨팅을 위한 센서 디바이스 Plug & Play)

  • Park, Jung-Sun;Eun, SeongBae;Yoon, Hyeon-Ju
    • IEMEK Journal of Embedded Systems and Applications
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    • v.7 no.3
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    • pp.151-156
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    • 2012
  • When mounting the sensor device in the way of Plug&Play, sensor device drivers need to be loaded and linked dynamically. Since a sensor node platform is based on small 8 bit MCU, dynamic loading and linking technique used in Windows and Linux can not be applied. In this paper, we present how to link and load dynamically sensor device drivers for sensor device Plug&Play. We implement a prototype and evaluate it to make sure that there is no performance degradation like sensor device driver connection speed and memory usage. Connection speed overhead increases to 0.2ms. Memory usage overhead increases to hundreds byte. It shows that there is no heavy influence in running the actual program.

A Study on the Behavior Analysis of the High Speed Rail System (한국형 고속전철 시스템엔지니어링 관리체계의 거동분석에 관한 연구)

  • 이태형;김대승;현승호
    • Proceedings of the KSR Conference
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    • 2001.10a
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    • pp.35.1-40
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    • 2001
  • This study is on the behavior analysis which can define and verify a system requirement through a behavior diagram for High speed rail system. The model considered in this study is limited to the preconditioning control of the control system specification for HSRS. To build an executable model, requirements should be decomposed first into leaf node requirements. The behavior model is composed of input, output, and functions which are linked with leaf node requirements. It is important that a single requirement must specify a single Auction. Using the developed executable model and the traceability between requirements and functions, this study found out a lot of static and dynamic inconsistency, missed and derived requirements. This is to develop and executable behavior model to do functional analysis and be able to verify the integrity of a specification.

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An Efficient Simulation of Discrete Time Queueing Systems with Markov-modulated Arrival Processes (MMAP 이산시간 큐잉 시스템의 속산 시뮬레이션)

  • Kook Kwang-Ho;Kang Sungyeol
    • Journal of the Korea Society for Simulation
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    • v.13 no.3
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    • pp.1-10
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    • 2004
  • The cell loss probability required in the ATM network is in the range of 10$^{-9}$ ∼10$^{-12}$ . If Monte Carlo simulation is used to analyze the performance of the ATM node, an enormous amount of computer time is required. To obtain large speed-up factors, importance sampling may be used. Since the Markov-modulated processes have been used to model various high-speed network traffic sources, we consider discrete time single server queueing systems with Markov-modulated arrival processes which can be used to model an ATM node. We apply importance sampling based on the Large Deviation Theory for the performance evaluation of, MMBP/D/1/K, ∑MMBP/D/1/K, and two stage tandem queueing networks with Markov-modulated arrival processes and deterministic service times. The simulation results show that the buffer overflow probabilities obtained by the importance sampling are very close to those obtained by the Monte Carlo simulation and the computer time can be reduced drastically.

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An Energy-Efficient Mobility-Supporting MAC Protocol in Wireless Sensor Networks

  • Peng, Fei;Cui, Meng
    • Journal of Communications and Networks
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    • v.17 no.2
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    • pp.203-209
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    • 2015
  • Although mobile applications are an essential characteristic of wireless sensor networks, most existing media access control (MAC) protocols focus primarily on static networks. In these protocols, fixed periodic neighbor discovery and schedule updating are used to connect and synchronize neighbors to provide successful data transmission; however, they cannot adapt to mobile speed variation and degrade the network performance dramatically. In this paper, we propose a mobile-supporting mechanism for MAC protocols, in which the decision to update the neighbors of a mobile node is made adaptively according to the mobile speed. Analysis and simulation results demonstrate that the mechanism efficiently avoids the disconnection of amobile node from its neighbors and achieves a better performance as compared with fixed periodic neighbor discovery.

MPLS Traffic Engineering of standard skill (MPLS Traffic Engineering의 표준 기술)

  • Kim, Kang;Jeon, Jong-Sik;Kim, Ha-Sik
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.4
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    • pp.68-73
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    • 2001
  • MPLS(Multi protocol Label Switching) is standard skill for added to speed and control the Network Traffic. MPLS concerned the routing protocol to relative Pack line, Each Pack composed label and node, saved the time to seek the address of node. MPLS worked IP, ATM and Network protocol of flame rely. MPLS is Network OSI suport model, 2Layer send to most of Packinsted of 3Layer Switching. MPLS is added speed Traffic of QoS and effective controled the Network.

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A Study on the Design of Monitoring and Control System Using 87C51 Microprocessor (87C51을 이용한 분산처리 감시 및 제어 시스템의 설계에 관한 연구)

  • Hong, Sun-Cheol;Jeong, Gyeong-Yeol
    • 연구논문집
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    • s.24
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    • pp.129-140
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    • 1994
  • Design and implementation of monitoring and control system using dual-microprocessor node is presented for real time process. The proposed system is implemented with 2 of the single chip microprocessors in tightly coupled mode and results in speed up of $s_p=1.74.$ Under the assumption that the nodes are interconnected in multidrop. the overall system performance such as average throughout-delay characteristics and effective throughput are analyzed using M/G/1 gueueing model, and results show that the proposed node can be used to medium sized distributed monitoring and control system.

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A High Speed LDPC Decoder Structure Based on the HSS (HSS 기반 초고속 LDPC 복호를 위한 구조)

  • Lee, In-Ki;Kim, Min-Hyuk;Oh, Deock-Gil;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.2
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    • pp.140-145
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    • 2013
  • This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

Implementation of Self-Adaptative System using Algorithm of Neural Network Learning Gain (신경회로망 학습이득 알고리즘을 이용한 자율적응 시스템 구현)

  • Lee, Sung-Su
    • Proceedings of the KIEE Conference
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    • 2006.07d
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    • pp.1868-1870
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    • 2006
  • Neural network is used in many fields of control systems, but input-output patterns of a control system are not easy to be obtained and by using as single feedback neural network controller. And also it is difficult to get a satisfied performance when the changes of rapid load and disturbance are applied. To resolve those problems, this paper proposes a new algorithm which is the neural network controller. The new algorithm uses the neural network instead of activation function to control object at the output node. Therefore, control object is composed of neural network controller unifying activation function, and it supplies the error back propagation path to calculate the error at the output node. As a result, the input-output pattern problem of the controller which is resigned by the simple structure of neural network is solved, and real-time learning can be possible in general back propagation algorithm. Application of the new algorithm of neural network controller gives excellent performance for initial and tracking response and it shows the robust performance for rapid load change and disturbance. The proposed control algorithm is implemented on a high speed DSP, TMS320C32, for the speed of 3-phase induction motor. Enhanced performance is shown in the test of the speed control.

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Design of High Speed LDPC Encoder Based on DVB-S2 Standard (DVB-S2 기반 고속 LDPC 부호기 설계)

  • Park, Gun Yeol;Lee, Seong Ro;Jeon, Sung Min;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.2
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    • pp.196-201
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    • 2013
  • In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

Probabilistic Assessment of Voltage Stability Margin in Presence of Wind Speed Correlation

  • Li, Hongxin;Cai, DeFu;Li, Yinhong
    • Journal of Electrical Engineering and Technology
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    • v.8 no.4
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    • pp.719-728
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    • 2013
  • Probabilistic assessment of voltage stability margin (VSM) with existence of correlated wind speeds is investigated. Nataf transformation is adopted to establish wind speed correlation (WSC) model. Based on the saddle-node bifurcation transversality condition equations and Monte Carlo simulation technique, probability distribution of VSM is determined. With correlation coefficients range low to high value, the effect of WSC on VSM is studied. In addition, two risk indexes are proposed and the possible threat caused by WSC is evaluated from the viewpoint of risk analysis. Experimental results show that the presence of correlated wind speeds is harmful to safe and stable operation of a power system as far as voltage stability is concerned. The achievement of this paper gives a detailed elaboration about the influence of WSC on voltage stability and provides a potentially effective analytical tool for modern power system with large-scale wind power sources integration.