• Korean Journal of Materials Research
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• v.10 no.12
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• pp.799-806
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• 2000

Cu$_{6}$Sn$_{5}$-dispersed 63Sn-37Pb solder bumps of 760$\mu\textrm{m}$ size were fabricated on Au(0.5$\mu\textrm{m}$)/Ni(5$\mu\textrm{m}$)/Cu(27$\pm$20$\mu\textrm{m}$) BGA substrates by screen printing process, and their shear strength were characterized with variations of dwell time at reflow peak temperature and aging time at 15$0^{\circ}C$ . With dwell time of 30 seconds at reflow peak temperature, the solder bumps with Cu$_{6}$Sn$_{5}$ dispersion exhibited higher shear strength than the value of the 63Sn-37Pb solder bump. With increasing the dwell time longer than 60 seconds, however the shear strength of the Cu$_{6}$Sn$_{5}$-dispersed solder bumps became lower than that the 63Sn-37Pb solder bumps. The failure surface of the solder bumps could be divided into two legions of slow crack propagation and critical crack propagation. The shear strength of the solder bumps was inversely proportional to the slow crack propagation length, regardless of the dwell time at peak temperature, aging time at 150 $^{\circ}C$ and the volume fraction of Cu$_{6}$Sn$_{5}$ dispersion.> 5/ dispersion.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.119-126
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• 2001

Chip-on-glass(COG) mounting of area array electronic packages was attempted by heating the rear surface of a contact pad film deposited on a glass substrate. The pads consisted of an adhesion(i.e. Cr or Ti) and a top coating layer(i.e. Ni or Cu) was heated by an UV laser beam transmitted through the glass substrate. The laser energy absorbed on the pad raised the temperature of a solder ball which is in physical contact with the pad, forming a reflowed solder bump. The effects of the adhesion and top coating layer on the laser reflow soldering were studied by measuring temperature profile of the ball during the laser heating process. The results were discussed based on the measurement of reflectivity of the adhesion layer. In addition, the microstructures of solder bumps and their mechanical properties were examined.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional Pt layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at $330^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.6
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• pp.181-186
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• 2007

UBM (Under Bump Metallurgy) of flip chip assemblies consists of several layers such as the solder wetting, the diffusion barrier, and the adhesion layers. In addition, IMC layers are formed between the solder wetting layers (e.g. Cu, Ni) and the solder. The primary failure mechanism of the solder joints in flip chips is widely known as the fatigue failure caused by thermal fatigues or electromigration damages. Sometimes, the premature brittle failure occurs in the IMC layers. However, these phenomena have thus far been viewed from only experimental investigations. In this sense, this paper presents a method for solid modeling of IMC layers in flip chip assemblies, thus providing a pre-processing tool for finite element analysis to simulate the IMC failure mechanism. The proposed modeling method is CSG-based and can also be applied to the modeling of UBM structure in flip chip assemblies. This is done by performing Boolean operations according to the actual sequences of fabrication processes

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional R layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at 330$^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• Journal of Welding and Joining
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• v.20 no.4
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• pp.505-509
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• 2002

Pb is considered to be eliminated from solder, due to its toxicity. However, melting temperatures of most Pb-free solders are known higher than that of Sn37Pb. Therefore, there is a difficulty to apply Pb-free solders to electronic industry. Since Sn3Ag8Bi5In has relatively lower melting range as $188~200^{\circ}C$, on this study. Wettability and soldering characteristics of Sn3Ag8Bi5In solder in BGA were investigated to solve for what kind of problem. Zero cross time, wetting time, and equilibrium force of Sn3Ag8Bi5In solder for Cu and plated Cu such as Sn, Ni, and Au/Ni-plated on Cu were estimated. Plated Sn on Cu showed best wettability for zero cross time, wetting time and equilibrium farce. Shear strength of the reflowed joint with Sn3Ag8Bi5In ball in BGA was investigated. Diameter of the ball was 0.5mm, UBM(under bump metallurgy) was $Au(0.5\mu\textrm{m})Ni(5\mu\textrm{m})/Cu(18\mu\textrm{m})$ and flux was RMA type. For the reflow soldering, the peak reflow temperature was changed in the range of $220~250^{\circ}C$, and conveyor speed was 0.6m/min.. The shear strength of Sn3Ag8Bi5In ball showed similar level as those of Sn37Pb. The soldered balls are aged at $110^{\circ}C$ for 36days and their shear strengths were evaluated. The shear strength of Sn3Ag8Bi5In ball was increased from 480gf to 580gf by aging for 5 days.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.9-16
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• 2005

This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.9-14
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• 2007

In this study, the thermal reliability on flip chip package with non-conductive pastes (NCPs) was evaluated under accelerated conditions. As the number of thermal shock cycle and the dwell time of temperature and humidity condition increased, the electrical resistance of the flip chip package with NCPs increased. These phenomenon was occurred by the crack between Au bump and Au bump and the delamination between chip or substrate and NCPs during the thermal shock and temperature and humidity tests. And the variation of electrical resistance during temperature and humidity test was larger than that during thermal shock test. Therefore it was identified that the flip chip package with NCPs was sensitive to environment with moisture.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.81-88
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• 2010

Thermal annealing and electromigration test were performed at $150^{\circ}C$ and $4{\times}10^3\;A/cm^2$ conditions in order to investigate the effect of PCB surface finishs on the growth kinetics of intermetallic compound (IMC) in Sn-3.0Ag-0.5Cu solder bump. The surface finishes of the electrodes of printed circuit board (PCB) were organic solderability preservation (OSP), immersion Sn, and electroless Ni/immersion gold (ENIG). During thermal annealing, the OSP and immersion Sn show similar IMC growth velocity, while ENIG surface finish had much slower IMC growth velocity. Applying electric current accelerated IMC growth velocity and showed polarity effect due to directional electron flow.

• Korean Journal of Materials Research
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• v.6 no.7
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• pp.700-708
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• 1996

Electroless plating technique was utilized to flip chip bonding to improve surface mount characteristics. Each step of plating procedure was studied in terms pf pH, plating temperature and plating time. Al patterned 4 inch Si wafers were used as substrstes and zincate was used as an activation solution. Heat treatment was carried out for all the specimens in the temperature range from room temperature to $400^{\circ}C$ for $30^{\circ}C$ minutes in a vacuum furnace. Homogeneous distribution of Zn particles of size was obtained by the zincate treatment with pH 13 ~ 13.5, solution concentration of 15 ~ 25% at room temperature. The plating rates for both Ni-P and Au electroless plating steps increased with increasing the plating temperature and pH. The main crystallization planes of the plated Au were found to be (111) a pH 7 and (200) and (111) at pH 9 independent of the annealing temperature.