• 전기전자학회논문지
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• 제24권1호
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• pp.170-177
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• 2020

본 논문은 HF/LF 변조 방법을 적용한 ANPC (active neutral point clamped) 인버터의 스위치 개방 고장에 대응하기 위한 허용 제어 방법을 제안한다. 기존 Si 기반 인버터에 비해 SiC MOSFET과 Si IGBT로 구성된 ANPC 인버터는 시스템의 효율이 높고 출력 품질이 우수하다. HF/LF 변조는 커뮤테이션 루프를 줄일 수 있어 MW 급 대용량 인버터를 위해 사용되는 변조 기법이다. MW 급 인버터의 스위치 개방 고장은 부하에 심각한 손상을 입히며, 인버터가 동작을 멈출 경우 막대한 경제적 손실을 야기한다. 제안하는 스위치 개방 고장의 허용 제어 기술은 ANPC 인버터의 지속적인 운전을 가능하게 하며 신뢰성을 향상 시킨다. 제안하는 기법의 성능은 시뮬레이션 결과를 통해 검증한다.

• Journal of Power Electronics
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• 제19권4호
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• pp.989-999
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• 2019

This paper proposes a fault-tolerant control strategy with finite control set model predictive control (FCS-MPC) based on hierarchical optimization for five-level H-bridge neutral-point-clamped (5L-HNPC) inverter-fed induction motor drives. Fault-tolerant operation is analyzed, and the fault-tolerant control algorithm is improved. Adopting FCS-MPC based on hierarchical optimization, where the voltage is used as the controlled objective, called model predictive voltage control (MPVC), the postfault controller is simplified as a two layer control. The first layer is the voltage jump limit, and the second layer is the voltage following control, which adopts the optimal control strategy to ensure the current following performance and uniqueness of the optimal solution. Finally, simulation and experimental results verify that 5L-HNPC inverter-fed induction motor drives have strong fault tolerant capability and that the FCS-MPVC based on hierarchical optimization is feasible.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.489-490
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• 2016

본 논문에서는 인버터 시스템의 가격을 줄이기 위해 3-레벨 NPC 인버터의 중성단에 하나의 션트 저항을 삽입함으로써 AC 전동기의 3상 전류를 획득하는 방법을 제안한다. 션트 저항으로부터 정확한 상 전류를 획득하기 위해서는 최소한의 시간이 필요하며 때문에 측정불가영역이 존재하게 된다. 기존의 측정불가영역으로 부터 상 전류를 복원하는 방법은 스위칭 패턴을 이동시키거나 공간 벡터 전압 변조 기법(SVPWM) 이외의 변조 기법을 이용하였는데 이러한 방법은 전류에 고조파를 증가시켜 효율을 떨어뜨리고 소음을 발생시킨다. 본 논문에서는 동기 좌표계 d-q축 비례적분제어기와 전동기 시스템의 전달함수를 이용하여 지령 전류로부터 실제 전류와 같은 전류를 얻는 방법을 통해 기존의 문제점들을 개선하는 방법을 제안한다. 제안된 방법은 시뮬레이션을 통해 증명하였다.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1872-1882
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• 2017

Medium voltage drive systems driven by high-power multi-level inverters operating at low switching frequency can reduce the switching losses of the power device and increase the output power. Employing subsection synchronous current harmonic minimum pulse width modulation (CHMPWM) technique can maintain the total harmonic distortion of current at a very low level. It can also reduce the losses of the system, improve the system control performance and increase the efficiency of DC-link voltage accordingly. This paper proposes a subsection synchronous CHMPWM approach of active neutral point clamped five-level (ANPC-5L) inverter under low switching frequency operation. The subsection synchronous scheme is obtained by theoretical calculation based on the allowed maximum switching frequency. The genetic algorithm (GA) is adopted to get the high-precision initial values. So the expected switching angles can be achieved with the help of sequential quadratic programming (SQP) algorithm. The selection principle of multiple sets of the switching angles is also presented. Finally, the validity of the theoretical analysis and the superiority of the CHMPWM are verified through both the simulation results and experimental results.

• Journal of Power Electronics
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• 제16권6호
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• pp.2109-2118
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• 2016

Based on the space vector pulse width modulation (SVPWM) theory, this paper realizes an easier SVPWM strategy, which is equivalently implemented by CBSPWM with zero-sequence voltage injection. The traditional SVPWM strategy has no effect on controlling the neutral-point voltage balance. In order to solve the neutral-point voltage unbalance problem for neutral-point-clamped (NPC) three-level inverters, this paper proposes a neutral-point voltage balance controller. The proposed controller realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the three-phase modulation waves of an equivalent SVPWM strategy. Compared with the traditional SVPWM strategy, the proposed neutral-point voltage balance controller has a strong ability to balance the neutral-point voltage, has good steady-state performance, improves the output waveforms quality and is easy for digital implementation. An experiment has been carried out on a NPC three-level inverter prototype based on a digital signal processor-complex programmable logic device (DSP-CPLD). The obtained experimental results verify the effectiveness of the proposed neutral-point voltage balance controller.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.63-69
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• 1998

A new current controlled PWM technique with NPC structure is proposed in this paper. A current controlled PWM technique with neutral-point-clamped pulse-width modulation inverter composed of main switching devices which operates as switch for PWM and auxiliary switching devices to clamp the output terminal potential to the neutral point potential is described. The proposed current controller has a first and second current band. The switching pattern will be made by the first current band. According to the second current band, the output state of the switching pattern is changed into positive and negative state. This inverter output contains less harmonic content and lower switching frequency than that of conventional current controlled PWM technique at the same current limit. Two inverters are compared analytically and the performance is investigated by the computer simulation.

• 전기전자학회논문지
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• 제24권3호
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• pp.867-876
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• 2020

본 논문에서는 3레벨 인버터로 구동되는 IPMSM의 고주파 주입 센서리스 운전에서 중성점 전압 리플 저감을 제안한다. 고주파 전압 주입 기반의 센서리스 제어는 IPMSM의 저속 영역에서 일반적으로 사용하는 센서리스 제어 기법이다. 고주파 전압 주입을 이용한 IPMSM의 센서리스 제어 과정에서 중성점에서의 전압 리플이 증가하는 문제가 발생한다. 중성점에서의 큰 전압 리플은 출력 전류를 왜곡시킬 뿐만 아니라 직류단 커패시터의 수명을 단축시키므로 저감되어야 한다. 본 논문에서 제안하는 기법은 지령 전압에 적절한 값을 보상하여 중성점 전압 리플을 저감하며, 보상값은 지령 전압과 전류를 이용하여 간단히 계산한다. 제안하는 중성점 전압 리플 저감 기법의 타당성은 시뮬레이션을 통해 검증한다.

• Journal of Power Electronics
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• 제19권3호
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• pp.702-713
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• 2019

Multilevel Inverters (MLIs) are widely used in medium voltage applications due to their various advantages. In addition, there are numerous types of MLIs for such applications. However, the diode-less 3-level (3L) T-type Neutral Point Clamped (NPC) MLI is the most advantageous due to its low conduction losses and high potential efficiency. The power circuit of a 3L T-type NPC is derived by the conventional two level inverter by a slight modification. In order to explore the MLI performance for various Pulse Width Modulation (PWM) schemes, this paper examines the operation of a 3L (five level line to line) T-type NPC MLI for various types of Multi-Carriers Pulse Width Modulation (MCPWM) schemes. These PWM schemes are compared in terms of their voltage profile, total harmonic distortion (THD) and conduction losses. In addition, a 3L T-type NPC MLI is also compared with the conventional NPC in terms of number of switches, clamping diodes, main diodes and capacitors. Moreover, the capacitor-balancing problem is also investigated using the Neutral Point Fluctuation (NPF) method with all of the MCPWM schemes. A 1kW 3L T-type NPC MLI is simulated in MATLAB/Simulink and implemented experimentally and its performance is tested with a 1HP induction motor. The results indicate that the 3L T-type NPC MLI has better performance than conventional NPC MLIs.

• Journal of Power Electronics
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• 제14권5호
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• pp.926-936
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• 2014

A simplified and effective space vector pulse-width modulation (SVPWM) algorithm with two and three levels for three-phase voltage-source converters is proposed in this study. The proposed SVPWM algorithm only uses several linear calculations on three-phase modulated voltages without any complicated trigonometric calculations adopted by conventional SVPWM. This simplified SVPWM also avoids choosing the vector sector required by conventional SVPWM. A two-level overmodulation scheme is integrated into the proposed two-level SVPMW to generate the output voltage that increases from a linear region to a six-step state with a smoothly linear transition characteristic and a simple overmodulation process without a lookup table and complicated nonlinear functions. The three-level SVPWM with a proportional-integral controller effectively balances the neutral point potential of the neutral point clamped converter. Results from the simulation in MATLAB/Simulink and the experiment based on a digital signal processor are provided to clearly demonstrate the validity and effectiveness of the proposed strategies.

• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.