• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.103-104
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• 2016

기존 Cascade H-bridge 인버터 토폴로지는 커패시터나 다이오드가 없이 스위치로 구성되어 있으며, 필터 없이 정현파와 유사하게 구현할 수 있다. 또한 출력전압 레벨이 높을수록 정현파와 유사하게 되어 고주파가 줄어들며, 각 셀을 직렬로 연결하면 입력전압보다 높은 출력전압 갖는다. 본 논문에서는 기존 Cascade H-bridge 인버터와 NPC(Neutral Point Clamped)가 결합한 Cascade H-bridge NPC 인버터를 제안하였다. Cascade H-bridge NPC 인버터는 기존 Cascade H-bridge 인버터 특성과 유사하며, Cascade H-bridge 인버터와 NPC 인버터의 장점을 가지고 있다. Cascade H-bridge 인버터와 Cascade H-bridge NPC 인버터를 시뮬레이션 통해 THD(Total Harmonic Distortion) 비교분석하였고 시뮬레이션은 PSIM 9.1.4을 가지고 검증하였다.

• 조명전기설비학회논문지
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• 제13권1호
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• pp.46-52
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• 1999

본 논문은 NPC 인버터의 구조를 위한 유도전동기 구동 시스템의 새로운 히스테리시스 전휴 제어기법을 제안하였다. 이러한 NPC 구조를 가지는 히스테리시스 전류제어 인버터의 구조는 각상의 인버터 출력전압을 제어하는 주 스위칭 소자와 주 스위치 OFF시에 출력전압을 0전위로 유지시키기 위한 보조 스위칭 소자로 구성된다. 이와 같이 제안된 HNPC (Hysteresis current controlled Neutral Point Clamped) 스위칭 기법은 1차, 2차 전류밴드를 가지며, 전압스위칭 신호는 1차 밴드와 실제전류의 비교 결과로서 발생하고, 2차 밴드와 실제전류의 비교 결과는 전압 스위칭 신호의 상위와 하위를 스위치의 동작을 결정하는 신호로서 동작한다. 이러한 스위칭의 결과로서 제안된 인버터 시스템의 출력 파형은 기존의 전류제어 방식과 비교하여 적은 고조파 성분의 함유특성을 가지고, 동일한 전류밴드 범위에서 낮은 스위칭 주파수를 가진다. 본 연구에서는 제안된 기법을 유도 전동기 구동 시스템에 적용하므로 이들 특성을 시뮬레이션을 통하여 고찰하였다.

• 조명전기설비학회논문지
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• 제29권9호
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• pp.71-80
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• 2015

This paper proposes a convenient thermal modeling method for loss distribution control method of 3-level Active NPC(Neutral Point Clamped) inverter. In the drawback of conventional 3-level NPC, the generated losses can occur unbalance in each switching device, as a result, thermal utilization of designed system has been decreased. In order to compensate unbalanced losses, Active NPC inverter performed loss balancing control with thermal modeling during operation of each switching device. Therefore, this paper deals with a convenient thermal modeling method based on newton's law of cooling rather than conventional thermal modeling method. Both simulation and experimental results based on 10kW 3-level Active NPC inverter confirm the validity of the analysis performed in the study.

• Journal of Power Electronics
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• 제5권3호
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• pp.224-232
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• 2005

A new three phase three-level Pulse Width Modulation (PWM) Switched Voltage Source (SVS) inverter with zero neutral point potential is proposed. It consists of three single-phase inverter modules. Each module is composed of a switched voltage source and inverter switches. The major advantage is that the peak value of the phase output voltage is twice as high as that of a conventional neutral-point-clamped (NPC) PWM inverter. Thus, the proposed inverter is suitable for applications with low voltage sources such as batteries, fuel cells, or solar cells. Furthermore, three-level waveforms of the proposed inverter can be achieved without the switch voltage imbalance problem. Since the average neutral point potential of the proposed inverter is zero, a common ground between the input stage and the output stage is possible. Therefore, it can be applied to a transformer-less Power Conditioning System (PCS). The proposed inverter is verified by a PSpice simulation and experimental results based on a laboratory prototype.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.42-45
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• 1997

A synchronous solid-state var compensator(SSVC) system which employs a three-phase neutral-point-darned (NPC) inverter is presented and analyzed for high voltage and high power applications. The proposed SSVC system can compensate for leading and lagging displacement factor. An optimal pulse-width-modulation (PWM) is used as a means of reducing the size of reactive components. A equivalent model is obtained using DQ-transform, and the characteristic of open-loop system are archived from DC and AC analyzes. A $\alpha$ phase-shift control is suggested using a self-controlled dc bus.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 추계학술대회 논문집
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• pp.11-16
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• 2003

The 3-level converter/inverter system is very efficient in the ac motor drives of high voltage and high power application. This paper proposed a simple method to diagnose faults using change of current vector pattern in space vector diagram when the faults occurrence in the 3-level inverter and a control method that can protect system from unbalance of the neutral point voltage according to faults. The validity of the proposed method is demonstrated by the simulation results.

• Journal of Power Electronics
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• 제18권1호
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1963-1965
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• 1998

In this paper, a new simplified configuration for a multi-level PWM inverter is proposed. The proposed inverter consists of an auxiliary circuit with one switching device, and 3 phase full-bridge inverter. The proposed inverter, in spite of reduction of the switching devices, offers characteristics similar to the NPC(Neutral - point - clamped)- PWM inverter. Also, since the reduction of the switching devices, the control strategy is simplified. And switching loss is reduced. In addition to, it is possible that reliable DC level voltage than former multi-level inverter. And load power application is same to conventional NPC-PWM inverter. The performance of the system is verified by simulation. In this paper, show the simulation result of the single phase full bridge inverter application.

• Journal of Power Electronics
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• 제19권3호
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.