• 전력전자학회논문지
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• 제19권4호
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• 전기학회논문지
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• 제66권5호
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• pp.778-785
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• 2017

This paper presents a control method for reducing the distortion of the grid current at a grid-connected three-level neutral point clamped (NPC) inverter. The grid current is distorted from the 5th and 7th harmonic components in the stationary frame current also the 6th harmonic component in the synchronous frame current. In this paper, the 6th harmonic component on synchronous frame is controlled by using all-pass filters (APFs) and proportional integral (PI) controllers for distortion of the grid side. When transformed the 6th harmonic component is controlled, the 5th and 7th harmonic components are reduced. The validity of the proposed control method is verified by simulation and experiment results using a 25kW three-level NPC inverter.

• Journal of Power Electronics
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• 제18권2호
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• pp.432-444
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• 2018

This paper presents a capacitor voltage balancing topology using a three-level boost converter (TLBC) for a neutral point clamped (NPC) three-level inverter fed surface permanent magnet synchronous motor drive (SPMSM). It enhanced the performance of the drive in terms of its voltage THD and torque pulsation. The main attracting feature of the proposed control is the boosting of the input voltage and at the same time the balancing of the capacitor voltages. This control also reduces the computational complexity. For the purpose of close loop vector control, a software based cost effective resolver to digital converter RDC-less estimation is implemented to calculate the speed and position. The proposed drive is simulated in the MATLAB/SIMULINK environment and an experimental investigation using dSPACE DS1104 validates the proposed drive system at different operating condition.

• 전력전자학회논문지
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• 제27권4호
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• pp.291-296
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• 2022

Capacitor is one of the reliability-critical components in power converters. The lifetime of the capacitor decreases as the operating temperature increases, and power losses caused by capacitor current are the main cause of the capacitor temperature increase. Therefore, various studies are being conducted to improve the lifetime of the capacitor by reducing the current of DC-link capacitors. In this study, pulse width modulation methods proposed for improving the lifetime of DC-link capacitors of the three-level NPC inverter are comparatively analyzed. The lifetime evaluation of the DC-link capacitor under different modulation methods is performed at component level first and then system level by considering all capacitors by applying Monte Carlo simulation. Furthermore, their effects on the efficiency and THD of the output current are also considered.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.315-316
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• 2015

본 논문에서는 3-레벨 Neutral-Point-Clamped (NPC) 인버터의 DC-Link 중성점 전압 리플을 저감하여 인버터 출력 전압의 품질 신뢰성 향상이 가능한 새로운 Discontinuous Pulse Width Modulation (DPWM) 기법을 제안한다. NPC 인버터에서는 두 개의 커패시터로 이루어진 DC-Link 구조로 인해 상, 하단 DC-Link 커패시터 전압 불평형인 상황에서 DC-Link 중 성점 전압 리플이 발생한다. 중성점 전압 리플 발생 시 출력 전압의 품질을 보장할 수 없으며, 민감한 부하에 손상을 입힐 수 있다. 제안한 DPWM 알고리즘은 DC-Link 커패시터 전압을 조정하는 두 개의 오프셋을 사용하여 중성점 전압 리플을 저감한다. 또한, 시뮬레이션을 통해 본 논문에서 제안한 알고리즘의 타당성을 검증한다.

• Journal of Power Electronics
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• 제16권4호
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• pp.1415-1425
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• 2016

This paper presents a new approach for fault diagnosis in three-level neutral point clamped inverters. The proposed method is based on the average values of the positive and negative parts of normalized output currents. This method is capable of detecting and locating multiple open-circuit faults in the controlled power switches of converters in half of a fundamental period of those currents. The implementation of this diagnostic approach only requires two output currents of the inverter. Therefore, no additional sensors are needed other than the ones already used by the control system of a drive based on this type of converter. Moreover, through the normalization of currents, the diagnosis is independent of the load level of the converter. The performance and effectiveness of the proposed diagnostic technique are validated by experimental results obtained under steady-state and transient conditions.

• Journal of Power Electronics
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• 제19권1호
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• pp.146-157
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• 2019

The inverter is an essential part of permanent magnet synchronous motor (PMSM) drive systems. The performance of an inverter is greatly influenced by its modulation strategy. Using a proper management of modulation strategies can guarantee high performance from a PMSM under various speed conditions. Switching between modulations is a pivotal technique that determines the performance of a PMSM. Most works on hybrid methods focus on two-level induction motors drive systems. In this paper, in order to improve the performance of PMSMs under various speed conditions, a hybrid method of a pulse width modulation (PWM) control scheme based on a neutral-point-clamped (NPC) three level topology was proposed. This hybrid PWM modulation comprised space vector PWM (SVPWM) and selective harmonic elimination PWM (SHEPWM). Under low speed conditions, the SVPWM is employed to cause the PMSM to start smoothly, and to obtain a rapid response from the control system. Under high speed conditions, the SHEPWM is employed to reduce the switching frequency and to eliminate particular current harmonics. Moreover, the harmonic characteristics of different modulations are analyzed to obtain a smooth transition between the SHEPWM and the SVPWM. Experimental and simulation results indicated the effectiveness of the proposed control method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.205-206
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• 2014

본 논문은 불평형 계통 조건하에 LCL필터를 사용한 3레벨 NPC 인버터의 모델링과 정지 좌표계에서 전류의 정상분과 역상분을 동시에 제어하여 인버터 시스템을 안정적으로 동작시키는 방법을 제안한다. 또한 본 논문은 NPC 인버터가 가지는 태생적인 문제점인 중성점 전압 밸런싱 문제를 간단히 계산 된 옵셋전압을 이용하여 해결한다. 제안된 방법은 시뮬레이션 결과를 통하여 타당성을 검증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.376-377
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• 2011

본 논문에서는 LCL 필터를 사용한 계통 연계형 3-레벨 인버터의 소신호 등가모델을 유도하는 과정과 이 모델을 이용한 계통 전류 및 중성점 전류 제어기를 설계하는 내용을 소개한다. 소신호 등가모델은 평균화 과정, 변동과 선형화 과정을 통해 유도하였다. 특히, 중성점 전류 제어기 설계를 위한 DC 링크단의 소신호 모델은 새로운 스위칭 함수를 적용시킴으로써 유도하였다. 제안된 방식의 검증을 위하여 시뮬레이션을 실시하였고 또한, 소용량 프로토타입을 제작하여 실험 결과를 통해 본 논문에서 제안한 모델링 및 제어기설계의 타당성을 입증하였다.

• Journal of Power Electronics
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• 제16권5호
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• pp.1964-1980
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• 2016

This paper presents a new simplified harmonics extraction algorithm based on the synchronous reference frame (SRF) for an indirect current controlled (ICC) three-level neutral point diode clamped (NPC) inverter-based shunt active power filter (SAPF). The shunt APF is widely accepted as one of the most effective current harmonics mitigation tools due to its superior adaptability in dynamic state conditions. In its controller, the SRF algorithm which is derived based on the direct-quadrature (DQ) theory has played a significant role as a harmonics extraction algorithm due to its simple implementation features. However, it suffers from significant delays due to its dependency on a numerical filter and unnecessary computation workloads. Moreover, the algorithm is mostly implemented for the direct current controlled (DCC) based SAPF which operates based on a non-sinusoidal reference current. This degrades the mitigation performances since the DCC based operation does not possess exact information on the actual source current which suffers from switching ripples problems. Therefore, three major improvements are introduced which include the development of a mathematical based fundamental component identifier to replace the numerical filter, the removal of redundant features, and the generation of a sinusoidal reference current. The proposed algorithm is developed and evaluated in MATLAB / Simulink. A laboratory prototype utilizing a TMS320F28335 digital signal processor (DSP) is also implemented to validate effectiveness of the proposed algorithm. Both simulation and experimental results are presented. They show significant improvements in terms of total harmonic distortion (THD) and dynamic response when compared to a conventional SRF algorithm.