• 한국생명과학회:학술대회논문집
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• 한국생명과학회 2006년도 제47회 학술심포지움 및 추계국제학술대회
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• pp.43.2-43.2
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• 2006

• 한국지능시스템학회논문지
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• 제26권5호
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• pp.368-374
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• 2016

본 논문에서 뉴런시냅스 응용을 위한 이산화 타이타늄 나노와이어 기반 멤리스터 소자의 전기회로 모델의 실험적 연구를 보인다. 제안하는 멤리스터 소자의 전기회로 모델은 IC 칩과 연산증폭기, 곱셈기 저항 및 커패시터 등의 수동소자 등으로 이루어진다. 멤리스터 소자의 등가모델의 시간파형, 주파수 특성, I-V 곡선 및 전력특성 등에 대한 PSPICE 모의실험 및 하드웨어 구현의 실험적 연구를 하였다. 측정결과, 히스테리시스 전류-전압 특성 등 실제 멤리스터 소자의 전기적 특성에 유사한 결과를 확인하였다.

• Biomolecules & Therapeutics
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• 제14권2호
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• pp.75-82
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• 2006

Synaptic plasticity, which is a long lasting change in synaptic efficacy, underlies many neural processes like learning and memory. It has long been acknowledged that new protein synthesis is essential for both the expression of synaptic plasticity and memory formation and storage. Most of the research interests in this field have focused on the events regulating transcriptional activation of gene expression from the cell body and nucleus. Considering extremely differentiated structural feature of a neuron in CNS, a neuron should meet a formidable task to overcome spatial and temporal restraints to deliver newly synthesized proteins to specific activated synapses among thousands of others, which are sometimes several millimeters away from the cell body. Recent advances in synaptic neurobiology has found that almost all the machinery required for the new protein translation are localized inside or at least in the vicinity of postsynaptic compartments. These findings led to the hypothesis that dormant mRNAs are translationally activated locally at the activated synapse, which may enable rapid and delicate control of new protein synthesis at activated synapses. In this review, we will describe the mechanism of local translational control at activated synapses focusing on the role of cytoplasmic polyadenylation of dormant mRNAs.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2001년도 추계학술대회 학술발표 논문집
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• pp.10-13
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• 2001

Nonlinear Function Approximation of Moduled Neural Network Using Genetic Algorithm Neural Network consists of neuron and synapse. Synapse memorize last pattern and study new pattern. When Neural Network learn new pattern, it tend to forget previously learned pattern. This phenomenon is called to catastrophic inference or catastrophic forgetting. To overcome this phenomenon, Neural Network must be modularized. In this paper, we propose Moduled Neural Network. Modular Neural Network consists of two Neural Network. Each Network individually study different pattern and their outputs is finally summed by net function. Sometimes Neural Network don't find global minimum, but find local minimum. To find global minimum we use Genetic Algorithm.

• 제어로봇시스템학회논문지
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• 제21권5호
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• 전자공학회논문지B
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• 제31B권4호
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• pp.155-165
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• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.531-531
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• 2000

The challenge is to control unstable nonlinear dynamic systems using only sparse feedback from the environment concerning its performance. The design of such controllers can be achieved by evolving neural networks. An evolutionary approach to train neural networks in realtime is proposed. Evolutionary strategies adapt the weights of neural networks and the threshold values of neuron's synapses. The proposed method has been successfully implemented for pole balancing problem.

• 대한전기학회논문지
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• 제43권5호
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• pp.861-865
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• 1994

By using Neural Networks, a 8$\times$8 Banyan network controller is designed and implemented. In order to solve internal blocking and output blocking, Winner-Take-All method is used. The longer queue takes higher priority. First-in-first-out method is used among the non-blocking cells in the queue selected.The required time to select a cell is 2.7 $\mu$sec for 155Mbps. The implemented controller using Xilinx FPGA chip selects cells within 2.5$\mu$sec.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• 센서학회지
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• 제27권1호
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• pp.64-67
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• 2018

A new CMOS neuron circuit for implementing bistable synapses with spike-timing-dependent plasticity (STDP) properties has been proposed. In neuromorphic systems using STDP properties, the short-term dynamics of the synaptic efficacies are governed by the relative timing of the pre- and post-synaptic spikes, and the efficacies tend asymptotically to either a potentiated state or to a depressed one on long time scales. The proposed circuit consists of a negative shifter, a current starved inverter and a schmitt trigger designed using 0.18um CMOS technology. The simulation result shows that the proposed circuit can reduce the total size of neurons, and the spike energy of the proposed circuit is much less compared to the conventional circuits.