• Journal of the Korean Institute of Intelligent Systems
• /
• v.16 no.5
• /
• pp.627-634
• /
• 2006

We have proposed the methods how to control the slope of CMOS inverter's characteristic and how to shift it in y axis. We control the MOS transistor threshold voltage for these methods. By observing that two transistors are in saturation region at the center of the CMOS inverter's characteristic, we have presented how to make the characteristic for one pole neuron. The circuit level simulation is used for verifying the proposed method. PSpice(OrCAD Co.) is used for circuit level simulation.

• 전자공학회논문지 IE
• /
• v.46 no.1
• /
• pp.16-22
• /
• 2009

Integrated circuit of a pulse-type neuron for Hodgkin-Huxley model is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Proposed pulse-type neuron model consist of input stage with summing function and pulse generating block which make neuron pulse above threshold value. Pulse generating circuit consist of several transistors, capacitors and negative resistor with a charge supply function. SPICE simulation results show that neuron pulse is generated above threshold current of 70 nA. Measurements of the fabricated pulse type neuron chip in condition of 5 V power supply are shown and compared with the simulated results.

• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.135-143
• /
• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.157.6-157
• /
• 2001

We estimated various neuron functions to construct of engineering neurons, which are the combination of sigmoid, linear, sine, quadric, double/single bended, soft max/minimum functions. These combinations are estimated by the property on the potential surface between the learning points, calculation speed, and learning convergence; because the surface depends on the inference ability of a neuron system; and speed and convergence are depend on the efficiency on the points of engineering applications. After the evaluating discussions, we can select more appropriate combination than original sigmoid function´s, which is single bended function and linear one. The combination ...

• Journal of Advanced Navigation Technology
• /
• v.15 no.2
• /
• pp.256-263
• /
• 2011

The nerve impulse is induced by the stimulation of neuron or axon, and this stimulated voltage decays along the propagation distance and time if it is subtreshold potential. This behavior can be estimated using the electrical equivalent circuit because it is very similar to propagation phenomenon of electrical circuit to which Ohm's law is applied. Therefore, I calculated various biometric parameters of body, and then analyzed the propagation behavior of stimulated potential voltage using the distributed parameters of electrical circuit in this paper.

• Journal of Sensor Science and Technology
• /
• v.27 no.1
• /
• pp.64-67
• /
• 2018

A new CMOS neuron circuit for implementing bistable synapses with spike-timing-dependent plasticity (STDP) properties has been proposed. In neuromorphic systems using STDP properties, the short-term dynamics of the synaptic efficacies are governed by the relative timing of the pre- and post-synaptic spikes, and the efficacies tend asymptotically to either a potentiated state or to a depressed one on long time scales. The proposed circuit consists of a negative shifter, a current starved inverter and a schmitt trigger designed using 0.18um CMOS technology. The simulation result shows that the proposed circuit can reduce the total size of neurons, and the spike energy of the proposed circuit is much less compared to the conventional circuits.

• PNF and Movement
• /
• v.5 no.1
• /
• pp.57-66
• /
• 2007

This review discusses the development of muscle receptors, in particular, that of muscle sensory neurons and monosynaptic stretch reflex circuit. The development of muscle sensory neurons and monosynaptic stretch reflex requires a series of steps including expression of neurotrophic transcriptional factors and their receptor. The monosynaptic stretch reflex circuit is unique neuronal circuit system, and highly precise synaptic connection systems. Thus, coordination of sensory-motor function in muscle receptors depend on the expression of distinct classes of molecular cues, and on the formation of selective synaptic connections between sensory-motor neurons and their target muscle. Recent neurotrophic and transcription factor expression studies have expanded our knowledge on how muscle sensory neuron is formed, and how sensory-motor system is developed.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.191-194
• /
• 2000

A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.

• Journal of IKEEE
• /
• v.8 no.2 s.15
• /
• pp.172-180
• /
• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• BMB Reports
• /
• v.48 no.4
• /
• pp.229-233
• /
• 2015

The central nervous system (CNS) controls food intake and energy expenditure via tight coordinations between multiple neuronal populations. Specifically, two distinct neuronal populations exist in the arcuate nucleus of hypothalamus (ARH): the anorexigenic (appetite-suppressing) pro-opiomelanocortin (POMC) neurons and the orexigenic (appetite-increasing) neuropeptide Y (NPY)/agouti-related peptide (AgRP) neurons. The coordinated regulation of neuronal circuit involving these neurons is essential in properly maintaining energy balance, and any disturbance therein may result in hyperphagia/obesity or hypophagia/starvation. Thus, adequate knowledge of the POMC and NPY/AgRP neuron physiology is mandatory to understand the pathophysiology of obesity and related metabolic diseases. This review will discuss the history and recent updates on the POMC and NPY/AgRP neuronal circuits, as well as the general anorexigenic and orexigenic circuits in the CNS. [BMB Reports 2015; 48(4): 229-233]