• ETRI Journal
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• v.28 no.4
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.19-26
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• 2020

Electrocardiogram (ECG) classification has become an essential task of modern day wearable devices, and can be used to detect cardiovascular diseases. State-of-the-art Artificial Intelligence (AI)-based ECG classifiers have been designed using various artificial neural networks (ANNs). Despite their high accuracy, ANNs require significant computational resources and power. Herein, three different ANNs have been compared: multilayer perceptron (MLP), convolutional neural network (CNN), and spiking neural network (SNN) only for the ECG classification. The ANN model has been developed in Python and Theano, trained on a central processing unit (CPU) platform, and deployed on a PYNQ-Z2 FPGA board to validate the model using a Jupyter notebook. Meanwhile, the hardware accelerator is designed with Overlay, which is a hardware library on PYNQ. For classification, the MIT-BIH dataset obtained from the Physionet library is used. The resulting ANN system can accurately classify four ECG types: normal, atrial premature contraction, left bundle branch block, and premature ventricular contraction. The performance of the ECG classifier models is evaluated based on accuracy and power. Among the three AI algorithms, the SNN requires the lowest power consumption of 0.226 W on-chip, followed by MLP (1.677 W), and CNN (2.266 W). However, the highest accuracy is achieved by the CNN (95%), followed by MLP (76%) and SNN (90%).

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.3
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• pp.381-387
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• 2011

Measurement controller that acquire and control and observe data from scattering sensors is organic with central control room. Therefore, measurement controller is efficient wireless network than wire network. But, serious problem is happened in security from outside if use wireless network. Therefore, this paper proposed suitable MS-WP cryptographic system to measurement control wireless network to augment network efficiency of measure controller. Result that implement proposed MS-WP cryptographic system by chip level and achieve a simulation, confirmed that 130% processing rate increase and system efficiency are increased double than AES algorithm. Proposed MS-WP cryptographic system augments security and is considered is suitable to measurement controller because that low power is possible and the processing speed is fast.

• Proceedings of the Korea Contents Association Conference
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• 2007.11a
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• pp.586-588
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• 2007

The Moore's law states that the number of transistors on a chip doubles about every 18 months. And it was reported that the network speed has been doubled about every 9 months. This indicates that computing power and network is no longer the obstacles for the high performance applications requiring terabits networks. We believe that the application motivates the network and vice versa. This presentation will introduce the GLORIAD which is the first ring network connecting six countries around the world and provides scientists with advanced networking tools that improve a communications and data exchange. The GLORIAD trans-Pacific link started its service on August 1, 2005. Since then, there has been remarkable demonstrations were performed through major conferences like Supercomputing Conference. This paper will introduce the global collaborative works on demonstrations of VMT, high energy physics, SDSS and HD video transmission during SC'06 in Tampa, FL.

• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.500-506
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• 1999

We designed and fabricated a bidirectional optical transceiver module for low cost access network. An integrated chip forming a pin-PD on an 1.3 urn FP-LD was assembled by flip-chip bonding on a Si optical bench, a single mode fiber with an angled end facet was aligned passively with the integrated chip on V-groove of Si-optical bench. Gaussian beam theory was applied to evaluate the coupling coefficients as a function of some parameters such as alignment distance, angle of fiber end facet, vertical alignment error. The theory is also used to search the bottle-neck between transmittance and receiving coupling efficiency in the bi-directional optical system. Tn this paper, we confirmed that reduction of coupling efficiency by the vertical alignment error between laser beam and fiber core axis can be compensated by controlling the fiber facet angle. In the fabrication of sub-module, a'||'&'||' we made such that the fiber facet have a corn shape with an angled facet only core part, the reflection of transmitted laser beam from the fiber facet could be minimized below -35 dE in alignment distance of 2: 30 /J.m. In the same condition, transmitted output power of -12.1 dEm and responsivity of 0.2. AIW were obtained.

• KIEE International Transactions on Electrophysics and Applications
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• v.11C no.4
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• pp.127-132
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• 2001

We describe the pulse forming of pulsed $CO_2$laser using multi-pulse superposition technique. A various pulse length, high duty cycle pulse forming network(PFN) is constructed by time sequence. That is, this study shows a technology that makes it possible to make various pulse shapes by turning on SCRs of three PFN modules consecutively at a desirable delay time with the aid of PIC one-chip microprocessor. The power supply for this experiment consists of three PFN modules. Each PFN module uses a capacitor, a pulse forming inductor, a SCR, a High voltage pulse transformer, and a bridge rectifier on each transformer secondary. The PFN modules operate at low voltage and drive the primary of HV pulse transformer. The secondary of the transformer has a full-wave rectifier, which passes the pulse energy to the load in a continuous sequence. We investigated laser pulse shape and duration as various trigger time intervals of SCRs among three PFN modules. As a result, we can obtain laser beam with various pulse shapes and durations from about 250 $mutextrm{s}$ to 600 $mutextrm{s}$.

• Smart Structures and Systems
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• v.8 no.1
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• pp.39-52
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• 2011

We are developing a biomimetic robot based on the Sea Lamprey. The robot consists of a cylindrical electronics bay propelled by an undulatory body axis. Shape memory alloy (SMA) actuators generate propagating flexion waves in five undulatory segments of a polyurethane strip. The behavior of the robot is controlled by an electronic nervous system (ENS) composed of networks of discrete-time map-based neurons and synapses that execute on a digital signal processing chip. Motor neuron action potentials gate power transistors that apply current to the SMA actuators. The ENS consists of a set of segmental central pattern generators (CPGs), modulated by layered command and coordinating neuron networks, that integrate input from exteroceptive sensors including a compass, accelerometers, inclinometers and a short baseline sonar array (SBA). The CPGs instantiate the 3-element hemi-segmental network model established from physiological studies. Anterior and posterior propagating pathways between CPGs mediate intersegmental coordination to generate flexion waves for forward and backward swimming. The command network mediates layered exteroceptive reflexes for homing, primary orientation, and impediment compensation. The SBA allows homing on a sonar beacon by indicating deviations in azimuth and inclination. Inclinometers actuate a bending segment between the hull and undulator to allow climb and dive. Accelerometers can distinguish collisions from impediment to allow compensatory reflexes. Modulatory commands mediate speed control and turning. A SBA communications interface is being developed to allow supervised reactive autonomy.

• Journal of Information Processing Systems
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• v.20 no.1
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• pp.116-130
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• 2024

In the Internet-of-Things (IoT) or blockchain-based network systems, secure keys may be stored in individual devices; thus, individual devices should protect data by performing secure operations on the data transmitted and received over networks. Typically, secure functions, such as a physical unclonable function (PUF) and fully homomorphic encryption (FHE), are useful for generating safe keys and distributing data in a network. However, to provide these functions in embedded devices for IoT or blockchain systems, proper inspection is required for designing and implementing embedded system-on-chip (SoC) modules through overhead and performance analysis. In this paper, a virtual platform (SoC VP) was developed that includes a secure key generation module with a PUF and FHE. The SoC VP platform was implemented using SystemC, which enables the execution and verification of various aspects of the secure key generation module at the electronic system level and analyzes the system-level execution time, memory footprint, and performance, such as randomness and uniqueness. We experimentally verified the secure key generation module, and estimated the execution of the PUF key and FHE encryption based on the unit time of each module.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.